Patents by Inventor Dongping Wu

Dongping Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090057810
    Abstract: A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section after generating the conductive structure.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 5, 2009
    Inventors: Victor Verdugo, Dongping Wu, Clemens Fitz
  • Publication number: 20080283910
    Abstract: An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.
    Type: Application
    Filed: May 15, 2007
    Publication date: November 20, 2008
    Applicant: QIMONDA AG
    Inventors: Lars Dreeskornfeld, Dongping Wu, Jessica Hartwich, Juergen Holz, Arnd Scholz
  • Publication number: 20080012067
    Abstract: A method of forming a transistor involves defining an active area by defining isolation trenches, the isolation trenches being adjacent to the active area, and forming a gate electrode after defining the isolation trenches. The gate electrode is formed by etching a gate groove in the active area selectively with respect to an insulating material filling the isolation trenches, etching the insulating material filling the isolation trenches at a portion adjacent to a channel such that a portion of the channel having the shape of a ridge with a top side and two lateral sides is uncovered, providing a gate insulating material on the top side and the lateral sides, and providing a conducting material on the gate insulating layer such that the gate electrode is disposed along the top side and the two lateral sides of the channel.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 17, 2008
    Inventor: Dongping Wu
  • Publication number: 20070187774
    Abstract: An integrated semiconductor structure includes an n-channel transistor at a surface of a semiconductor body. The n-channel transistor includes a polysilicon gate overlying a first gate dielectric. A p-channel transistor is also formed at the surface of the semiconductor body. The p-channel transistor includes an n-doped polysilicon gate overlying a second gate dielectric. The second gate dielectric includes an aluminum oxide layer between an underlying dielectric layer and the n-doped polysilicon gate.
    Type: Application
    Filed: April 9, 2007
    Publication date: August 16, 2007
    Inventors: Matthias Goldbach, Dongping Wu
  • Patent number: 7202535
    Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: April 10, 2007
    Assignee: Infineon Technologies AG
    Inventors: Matthias Goldbach, Dongping Wu
  • Publication number: 20070015325
    Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure.
    Type: Application
    Filed: July 14, 2005
    Publication date: January 18, 2007
    Inventors: Matthias Goldbach, Dongping Wu
  • Publication number: 20060226473
    Abstract: A gate electrode stack is disposed on a substrate in a semiconductor device. A gate conductor includes at least one layer of polysilicon and at least one layer of poly-Si1?x,Gex material. The invention is also concerned with a process. This structure can be etched effectively since an end point detection is enabled.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 12, 2006
    Inventors: Dongping Wu, Matthias Goldbach, Ulrich Egger