Patents by Inventor DongSam Park
DongSam Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11823973Abstract: A semiconductor device has a substrate and two semiconductor die disposed over the substrate. A thermal interface material is disposed over the semiconductor die. A conductive epoxy is disposed on a ground pad of the substrate. A lid is disposed over the semiconductor die. The lid includes a sidewall over the ground pad between the semiconductor die. The lid physically contacts the conductive epoxy and thermal interface material.Type: GrantFiled: October 15, 2021Date of Patent: November 21, 2023Assignee: STATS ChipPAC Pte. Ltd.Inventors: DongSam Park, KyungOe Kim, WooJin Lee
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Publication number: 20230260865Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: KyungOe Kim, Wagno Alves Braganca, JR., DongSam Park
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Patent number: 11670563Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.Type: GrantFiled: June 24, 2021Date of Patent: June 6, 2023Assignee: STATS ChipPAC Pte. Ltd.Inventors: KyungOe Kim, Wagno Alves Braganca, Jr., DongSam Park
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Publication number: 20230119942Abstract: A semiconductor device has a substrate and two semiconductor die disposed over the substrate. A thermal interface material is disposed over the semiconductor die. A conductive epoxy is disposed on a ground pad of the substrate. A lid is disposed over the semiconductor die. The lid includes a sidewall over the ground pad between the semiconductor die. The lid physically contacts the conductive epoxy and thermal interface material.Type: ApplicationFiled: October 15, 2021Publication date: April 20, 2023Applicant: STATS ChipPAC Pte. Ltd.Inventors: DongSam Park, KyungOe Kim, WooJin Lee
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Publication number: 20220415744Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Applicant: STATS ChipPAC Pte. Ltd.Inventors: KyungOe Kim, Wagno Alves Braganca, JR., DongSam Park
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Publication number: 20150325553Abstract: A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Applicant: STATS CHIPPAC, LTD.Inventors: DongSam Park, YongDuk Lee
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Patent number: 9087701Abstract: A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.Type: GrantFiled: April 30, 2011Date of Patent: July 21, 2015Assignee: STATS ChipPAC, Ltd.Inventors: DongSam Park, YongDuk Lee
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Patent number: 8970044Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate.Type: GrantFiled: June 23, 2011Date of Patent: March 3, 2015Assignee: STATS ChipPAC Ltd.Inventors: A Leam Choi, DongSam Park, YongDuk Lee
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Patent number: 8883561Abstract: A semiconductor device has a carrier or first conductive layer with a plurality of TSV semiconductor die mounted over the carrier or first conductive layer. An encapsulant is deposited around the first semiconductor die and over the carrier or first conductive layer to embed the first semiconductor die. A conductive TMV is formed through the encapsulant. A second conductive layer is formed over a first surface of the encapsulant. A first insulating layer is formed over the first surface of the encapsulant while exposing portions of the second conductive layer. A second insulating layer is formed over the second surface of the encapsulant while exposing portions of the first conductive layer. Alternatively, a first interconnect structure is formed over the first surface of the encapsulant. The carrier is removed and a second interconnect structure is formed over a second surface of the encapsulant.Type: GrantFiled: April 30, 2011Date of Patent: November 11, 2014Assignee: STATS ChipPAC, Ltd.Inventors: DongSam Park, YongDuk Lee
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Patent number: 8704365Abstract: An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity.Type: GrantFiled: July 20, 2011Date of Patent: April 22, 2014Assignee: STATS ChipPAC Ltd.Inventors: DongSam Park, Dongjin Jung
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Patent number: 8598034Abstract: A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.Type: GrantFiled: November 16, 2012Date of Patent: December 3, 2013Assignee: STATS ChipPac Ltd.Inventors: DongSam Park, JoungIn Yang
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Patent number: 8460968Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stack substrate with a component side; connecting an integrated circuit component to the component side; attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component; forming a protection layer on a top and sides of the protruded end, the protection layer having a width equal to a width of the conductive post; applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and mounting a base package under the stack substrate, base package connected to the stack substrate.Type: GrantFiled: September 17, 2010Date of Patent: June 11, 2013Assignee: Stats Chippac Ltd.Inventors: DongSam Park, HanGil Shin, HeeJo Chi
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Publication number: 20130075933Abstract: A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.Type: ApplicationFiled: November 16, 2012Publication date: March 28, 2013Inventors: DongSam Park, JoungIn Yang
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Patent number: 8367465Abstract: A integrated circuit package on package system is provided including providing a base substrate having a base stackable connection, attaching a base integrated circuit on the base substrate, forming a stackable package including the base integrated circuit encapsulated with the base stackable connection partially exposed, and attaching a bottom package on the stackable package.Type: GrantFiled: March 17, 2006Date of Patent: February 5, 2013Assignee: STATS Chippac Ltd.Inventors: DongSam Park, Choong Bin Yim, In Sang Yoon
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Publication number: 20120326325Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate.Type: ApplicationFiled: June 23, 2011Publication date: December 27, 2012Inventors: A Leam Choi, DongSam Park, YongDuk Lee
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Patent number: 8334601Abstract: A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.Type: GrantFiled: June 27, 2011Date of Patent: December 18, 2012Assignee: Stats Chippac Ltd.Inventors: DongSam Park, Joungln Yang
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Publication number: 20120273960Abstract: A semiconductor device has a carrier or first conductive layer with a plurality of TSV semiconductor die mounted over the carrier or first conductive layer. An encapsulant is deposited around the first semiconductor die and over the carrier or first conductive layer to embed the first semiconductor die. A conductive TMV is formed through the encapsulant. A second conductive layer is formed over a first surface of the encapsulant. A first insulating layer is formed over the first surface of the encapsulant while exposing portions of the second conductive layer. A second insulating layer is formed over the second surface of the encapsulant while exposing portions of the first conductive layer. Alternatively, a first interconnect structure is formed over the first surface of the encapsulant. The carrier is removed and a second interconnect structure is formed over a second surface of the encapsulant.Type: ApplicationFiled: April 30, 2011Publication date: November 1, 2012Applicant: STATS CHIPPAC, LTD.Inventors: DongSam Park, YongDuk Lee
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Publication number: 20120273959Abstract: A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.Type: ApplicationFiled: April 30, 2011Publication date: November 1, 2012Applicant: STATS CHIPPAC, LTD.Inventors: DongSam Park, YongDuk Lee
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Publication number: 20120068332Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a stack substrate with a component side; connecting an integrated circuit component to the component side; attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component; forming a protection layer on a top and sides of the protruded end, the protection layer having a width equal to a width of the conductive post; applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and mounting a base package under the stack substrate, base package connected to the stack substrate.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Inventors: DongSam Park, HanGil Shin, HeeJo Chi
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Patent number: 8110905Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base integrated circuit, by: providing a metal sheet, mounting an integrated circuit die on the metal sheet, injecting a molded package body on the integrated circuit die and the metal sheet, and forming a ball pad, a bond finger, or a combination thereof from the metal sheet that is not protected by the molded package body; coupling a circuit package on the ball pad; and forming a component package on the substrate, the base integrated circuit, and the leadframe interposer.Type: GrantFiled: December 4, 2008Date of Patent: February 7, 2012Assignee: Stats Chippac Ltd.Inventors: DongSam Park, YoungSik Cho, Sang-Ho Lee