Abstract: A pixel circuit includes: a compensation circuit connected to a data line, a first gate line, and a second gate line, and configured to receive first and second voltages alternately through the data line, a first gate signal through the first gate line, and a second gate signal through the second gate line; a light-emitting element; a driving element including a gate electrode configured to receive the second voltage via the compensation circuit, the driving element being configured to generate a current to drive the light-emitting element; and a switch element including a gate electrode configured to receive the second gate signal via the compensation circuit, and configured to switch a path of the current between the driving element and the light-emitting element. The light-emitting element, the driving element, and the switch element may be connected in series between a first power line and a second power line.

Abstract: A display device includes a display panel configured to display an image, a plurality of cooling elements disposed in a matrix form to cool the heat generated by the display panel, a driver configured to drive the display panel and the cooling elements, and a timing controller configured to control the driver, wherein the timing controller is further configured to extract a data value for each area of the display panel based on a data signal and to generate a control signal for driving the cooling elements based on the data value.

Abstract: A display device includes a display panel including a subpixel connected to a power line, a data line, and a reference line; a power supply configured to supply power to the display panel through the power line; a data driver including a driving circuit configured to supply a data voltage to the display panel through the data line, and a sensing circuit configured to sense the display panel through the reference line; and a timing controller configured to control the power supply and the data driver, wherein the sensing circuit may have a variable sampling point for sensing the display panel in response to a change in a level of the power.

Abstract: A gate driving circuit may include a gate signal generating circuit configured to sequentially output at least one gate signal having a square wave pulse, and a ramp voltage generating circuit configured to receive the at least one gate signal and a slope data voltage to output a ramp voltage signal including a ramp waveform based on the square wave pulse of the at least one gate signal and on the slope data voltage.

Abstract: A display apparatus includes a display panel configured to display an image, a timing controller configured to control the display panel, and a power supply including an output circuit configured to generate an output power for supplying power to the display panel based on an input power, and an output controller configured to sense a voltage output through an output terminal of the output circuit to obtain a sensing value. The output controller provides a reference voltage value and compensation voltage values having levels which differ from a level of the reference voltage value, based on an external signal. Further, the output controller selectively outputs at least one of the reference voltage value and the compensation voltage values to provide a voltage value, based on the external signal, and generates a control signal for controlling the output circuit, based on the sensing value and the voltage value.

Abstract: A data transceiver system includes an encoder which generates first encoded data by performing a logical operation based on a random number and image data, and generates second encoded data by inverting the first encoded data every N bits, where N is a positive integer greater than or equal to 2, and a decoder which restores the first encoded data by decoding the second encoded data, and restores the image data by decoding the first encoded data.

Abstract: A power control device of a display apparatus includes a display panel configured to include a plurality of pixels, a panel driver configured to drive the display panel, a power control unit configured to output a power control signal into which one or more pieces of control command data are encoded, and a power source unit configured to shift an output level of a source voltage needed for an operation of each of the display panel and the panel driver, based on the control command data, wherein the control command data comprises a plurality of control pulses where a logic low period and a logic high period are alternated, and the logic low period is implemented with two or more different lengths.

Abstract: A display panel includes a plurality of pixels. Each of the pixels includes a first transistor having a gate electrode connected to a first node and a first electrode to which a high level driving voltage is applied, a light emitting device having an anode electrode connected to a second electrode of the first transistor and a cathode electrode to which a low level driving voltage is applied, a second transistor applying a fixing voltage to the first node based on a first gate signal, a third transistor applying a data voltage to a second node based on the first gate signal, a fourth transistor connecting the second node to an input terminal for the low level driving voltage based on a second gate signal having a phase opposite to a phase of the first gate signal, and a capacitor between the first node and the second node.

Abstract: An assistive system according to an embodiment of the present disclosure includes a cradle module including a holder body on which a user terminal is to be placed and a drive unit configured to drive the holder body, the cradle module configured to output a terminal connection signal when the user terminal is placed on the holder body, and an assistant server configured to receive the terminal connection signal from the cradle module and execute an assistive service, the assistant server configured to control the drive unit by a preset drive pattern through a drive control signal when executing the assistive service. It is possible to easily and conveniently identify a plurality of assistive services outputted according to each situation by controlling a cradle module through a drive pattern corresponding to an assistive service while outputting a voice corresponding to the assistive service when executing the assistive service.

Abstract: The present disclosure provides an all-in-one image quality improvement model providing method, which restores quality of images degraded due to multiple image quality degradation factors and is performed by a server, including collecting low-quality images of which image quality is degraded due to at least one of the multiple image quality degradation factors and determining an image quality degradation factor that is a cause of image quality degradation of a corresponding image, constructing an integrated restoration network and a single restoration network to restore the low-quality images with respect to the determined image quality degradation factors.

Abstract: A data receiver, which communicates with a data transmitter through a plurality of lanes, includes: a first reception unit which receives first data through a first lane; a second reception unit which receives second data through a second lane; and a detector which compares the first data and the second data to detect a skew between the first lane and the second lane. The first reception unit includes a first clock data recovery unit which recovers a first clock and first payload data from the first data. The first reception unit controls a loop speed of the first clock data recovery unit based on a skew level of the skew.

Abstract: A transmitter includes a transmission controller which outputs original data through an original data lane, an encoder which encodes the original data into encoded data and outputs the encoded data through an encoded data lane, and a transmission driver which outputs the encoded data at a speed of M (M is a real number greater than 0) gigabits per second through a transmission and reception interface. The transmission driver provides a first clock signal corresponding to an output speed to the encoder, the encoder provides a second clock signal having a second frequency less than a first frequency of the first clock signal to the transmission controller, the transmission controller outputs the original data based on the second clock signal, and the encoder outputs the encoded data based on the first clock signal.

Abstract: An electronic device includes a host processor including a data transmitter, a driving driver, and a display panel. The data transmitter includes a phase locked loop that generates a first clock and a second clock, a clock block that receives the first clock, a plurality of data blocks that receives the second clock, a first buffer connected between the phase locked loop and the clock block, and a plurality of second buffers respectively connected between the phase locked loop and the plurality of data blocks, and the first buffer and each of the plurality of second buffers may be activated or deactivated depending on an interface mode.

Abstract: A transceiver device includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload to generate a first payload in the second mode, and transmits a clock training pattern and the first payload through the first line and the second line. The receiver decodes the first payload and outputs reception data corresponding to the original payload in the second mode.

Abstract: A light emitting display device can include a display panel configured to display an image, a driver configured to drive the display panel, and a power supply configured to supply a high-level voltage to a first power line of the display panel. Also, the power supply includes a voltage controller configured to receive, from the driver, a vertical synchronization signal and current amount information of the high-level voltage for driving of the display panel, and boost the high-level voltage to be supplied to the display panel during a vertical blank period, based on the vertical synchronization signal and the current amount information of the high-level voltage.

Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1?1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1?1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.

Abstract: A pixel circuit, a display device, and a mobile terminal including the display device are disclosed. The pixel circuit includes one or more first switch elements configured to be turned on in response to a first gate signal; one or more second switch elements configured to be turned on in response to a second gate signal; one or more third switch elements configured to be turned on in response to a third gate signal; an internal gate signal generator configured to receive the first gate signal and the second gate signal to output the third gate signal; and a driving element configured to drive a light emitting element.

Abstract: An electroluminescence display apparatus includes a display panel including a plurality of pixels connected to a first power line, a power circuit converting a final feedback driving voltage input through a first input terminal thereof to output a high level driving voltage to a first position of the first power line through a first output terminal thereof, and a feedback control circuit receiving the high level driving voltage as a first feedback driving voltage, receiving a second feedback driving voltage from a second position of the first power line, and supplying the first input terminal of the power circuit with the final feedback driving voltage adjusted based on a first output contribution rate of the first feedback driving voltage and a second output contribution rate of the second feedback driving voltage.

Abstract: A transceiver includes a transmitter and a receiver which are connected to each other through a first line and a second line. The transmitter transmits a first clock training pattern to the receiver in a first period, transmits a second clock training pattern and a first first payload to the receiver in a second period, and transmits a third clock training pattern and a second first payload to the receiver in a third period. The first clock training pattern, the second clock training pattern, and the third clock training pattern are variable based on a plurality of driving modes.

Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals each having a first voltage range to the first line and the second line in a first mode, and signals each having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The receiver includes a low-power driver which receives signals through the first line and the second line in an operating state of the first mode, and stops an operation thereof in the second mode, and a high-speed driver which receives signals through the first line and the second line in the second mode, and stops an operation thereof in the first mode.