Abstract: A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.

Abstract: A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.

Abstract: A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.

Abstract: An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the inventive equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver. In some embodiments useful for equalizing a differential input signal, the equalizer includes two differential pairs of MOS transistors and a controllable current source determines the tail current for each differential pair. The current sources are independently controllable.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A heat sink assembly includes a heat sink (20) and a pair of clips (10) attached on opposite sides of the heat sink for securing the heat sink to an electronic component (40). The heat sink includes a base (22) and a plurality of fins (24). A pair of protrusions (28) is formed on bottom portions of adjacent two fins. A locking slot (29) is therefore formed between the base, the two adjacent fins, and the protrusions. The clip includes a pressing portion (12) squeenzedly received in the locking slot, a pair of extension portions (14) extending from opposite ends of the pressing portion, and a pair of hooks (16) formed on free ends of the extension portions. When the clips are deformed to cause the hooks to engage with the electronic component, the pressing portions of the clips press the heat sink toward the electronic component.

Abstract: A fuel cell system includes a fuel cell stack; a diluted fuel tank for storing diluted fuel; a diluted fuel conduit for supplying the diluted fuel from the fuel dilution tank to the fuel cell stack; a differential pressure sensor in the diluted fuel conduit to sense a differential pressure resulting from a fuel flow inside the diluted fuel conduit and to transmit an electric signal; and a controller for receiving the electric signal from the differential pressure sensor and for determining whether or not fuel is flowing inside the diluted fuel conduit.

Abstract: A combination of fan and heat sink includes a fan (10), a heat sink (20) and four fixtures (30). The fan defines four holes (12) in four corners thereof respectively. The heat sink has a plurality of parallel fins (24). Each fixture includes a post (32) inserted into the corresponding hole of the fan, a pressing portion (36) pressing the fan toward the heat sink and a locking leg (34) interlocking with outmost fins.

Abstract: A heat sink clip assembly (1) for attaching a heat sink (5) on a CPU (7) includes a retention frame (10), and a pair of clips (20) pivotally attached to two sides of the retention frame. Each clip includes a main body (21), and a handle (41) pivotally attached to the main body. The main body includes a cross beam (23), and two locking arms (31) respectively depending from opposite ends of the cross beam. Each locking arm defines a locking hole (33) at a distal end. The handle has a cam portion (47) at one end thereof. The clips are pivoted outwardly to make way for the heat sink to seat on the CPU. Then the clips are pivoted upwardly, so that the cross beam is suspended above the heat sink. The handle is pivoted downwardly so that the cam portion presses the heat sink to the CPU.

Abstract: In some embodiments, a device detection circuit for detecting whether a device is coupled to a differential link, a transmitter (e.g., a transceiver) including such a circuit, and a system including such a transmitter. Preferably, the device detection circuit includes two branches (each branch including a switch), a current source that causes current to flow through either branch, or to be shared by both branches, depending on the state of each switch, and a voltage swing detector configured to detect the voltage between a node (of one branch) and a node (of the other branch) during a device detection operation. In other embodiments, the invention is a device (e.g., a receiver) including a differential termination that can be coupled to a differential link, and an electrical overstress protection circuit coupled to the termination and configured to protect the device against electrical stress during a hot plug event.

Abstract: A heat dissipation assembly includes a heat sink (20), a backplate (50), a pair of posts (60) and a fastener (10). The heat sink is attached on a CPU (30) which is mounted on a PCB (40). The backplate is disposed below the PCB. The fastener includes a main body (14) spanning on the heat sink, a resilient member (16) and an operating member (12). The posts extends through the backplate and engaged with the main body. Before the fastener is activated, the resilient member and the operating member squeezes the main body therebetween. When the fastener is activated, the operating member is above the main body. The resilient member resiliently presses the heat sink toward the CPU and the main body with opposite directional forces. The posts are consequently forced by the main body to urge the backplate against the PCB.

Abstract: A heat dissipation assembly includes a heat sink (20), a backplate (50), a pair of posts (60) and a fastener (10). The heat sink is attached on a CPU (30) which is mounted on a PCB (40). The backplate is disposed below the PCB. The fastener includes a main body (14) spanning on the heat sink, a resilient member (16) and an operating member (12). The posts extends through the backplate and engaged with the main body. Before the fastener is activated, the resilient member and the operating member squeezes the main body therebetween. When the fastener is activated, the operating member is above the main body. The resilient member resiliently presses the heat sink toward the CPU and the main body with opposite directional forces. The posts are consequently forced by the main body to urge the backplate against the PCB.

Abstract: A heat dissipation assembly includes a heat sink (10), a fan (70), and a mounting device for attaching the fan to the heat sink. The mounting device includes four clips (30), and four shafts (50) pivotably connecting the clips to the heat sink. Each clip includes a main body (31), a top pressing portion (39), and a bottom mounting portion (43). A tab (45) is upwardly formed from a center of the mounting portion. Two parallel connecting portions (33) extend outwardily from two side edges of the main body respectively. The tabs of the mounting portions of the clips abut against the fan in corresponding through holes (72) thereof. The pressing pardons of the clips press an upper face of the fan at corresponding through holes thereof. Thus the fan is securely mounted on the heat sink between the pressing portion and the mounting portion of each of the clips.

Abstract: A heat sink assembly includes a heat sink (20) and a pair of clips (10) attached on opposite sides of the heat sink for securing the heat sink to an electronic device (30). The heat sink includes a base (22) and a plurality of fins (24). A pair of protrusions (28) is formed on bottom portions of adjacent two fins. A locking slot (29) is therefore formed between the base, the two adjacent fins, and the protrusions. The clip includes a pressing portion (12) squeenzedly received in the locking slot, a pair of extension portions (14) extending from opposite ends of the pressing portion, and a pair of hooks (16) formed on free ends of the extension portions. When the clips are deformed to cause the hooks to engage with the electronic device, the pressing portions of the clips press the heat sink toward the electronic device.

Abstract: A combination of fan and heat sink includes a fan (10), a heat sink (20) and four fixtures (30). The fan defines four holes (12) in four comers thereof respectively. The heat sink has a plurality of parallel fins (24). Each fixture includes a post (32) inserted into the corresponding hole of the fan, a pressing portion (36) pressing the fan toward the heat sink and a locking leg (34) interlocking with outmost fins.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.