Patents by Inventor Doohwan Lee

Doohwan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11581263
    Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: February 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choongbin Yim, Jungwoo Kim, Jihwang Kim, Jungsoo Byun, Jongbo Shim, Doohwan Lee, Kyoungsei Choi, Junggon Choi, Sungeun Pyo
  • Publication number: 20220310577
    Abstract: A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.
    Type: Application
    Filed: October 14, 2021
    Publication date: September 29, 2022
    Inventors: DOOHWAN LEE, SEOKHYUN LEE, JEONGHO LEE
  • Patent number: 11444706
    Abstract: Disclosed is an antenna module, which include a first antenna element, a second antenna element, and a communication module that includes a first transmit path and a first receive path connected with the first antenna element, a second transmit path and a second receive path connected with the second antenna element, and a detection circuit connected with at least a part of the second receive path. The communication module may output a specified signal by using the first transmit path and the first antenna element based at least on obtaining a request for identifying a state of the antenna module from an external device, may obtain the output specified signal by using the second receive path and the second antenna element, may identify an intensity of the obtained specified signal by using the detection circuit, and may determine whether the antenna module is abnormal, based at least on the intensity of the obtained specified signal.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: September 13, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongil Yang, Seonjun Kim, Jonghyun Park, Doohwan Lee, Jongin Lee
  • Publication number: 20220278049
    Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.
    Type: Application
    Filed: May 19, 2022
    Publication date: September 1, 2022
    Inventors: Joonsung Kim, Doohwan Lee, Taeho Ko, Bongsoo Kim, Seokbong Park
  • Publication number: 20220278011
    Abstract: Provided is method of manufacturing a semiconductor device. The method includes: forming a metal layer on a carrier; forming a conductor pattern layer on the metal layer; mounting a semiconductor chip on a tape; forming an encapsulant covering the semiconductor chip; attaching the conductor pattern layer to the encapsulant; removing the tape; and forming a connection structure electrically connected to the semiconductor chip in an area from which the tape is removed.
    Type: Application
    Filed: May 20, 2022
    Publication date: September 1, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunghawn BAE, Doohwan LEE, Jooyoung CHOI
  • Publication number: 20220262777
    Abstract: A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.
    Type: Application
    Filed: October 26, 2021
    Publication date: August 18, 2022
    Inventors: DOOHWAN LEE, Wonkyoung CHOI, JEONGHO LEE
  • Patent number: 11411325
    Abstract: In an OAM multiplexing communication system in which an M-UCA is provided in each of a transmitting station and a receiving station, signals in a plurality of OAM modes are generated and transmitted from each UCA of the transmitting station, signals in the plurality of OAM modes are received and demultiplexed by each UCA of the transmitting station, and streams of the number of UCAs×the number of OAM modes are subjected to spatial multiplex transmission, in which the transmitting station includes a signal processing unit generating the streams to be transmitted in the plurality of OAM modes from each of the UCAs of the M-UCA, and the receiving station includes a signal processing unit receiving the signals in the plurality of OAM modes demultiplexed by each of the UCAs of the M-UCA, and demultiplexes the received signals for each stream from signals in an identical OAM mode.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 9, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Doohwan Lee, Hirofumi Sasaki, Hiroyuki Fukumoto, Hiroyuki Shiba
  • Publication number: 20220230912
    Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dowan KIM, Doohwan LEE, Seunghwan BAEK
  • Publication number: 20220209810
    Abstract: The disclosure relates to an electronic device and a method for wireless communication including a power amplification circuit.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 30, 2022
    Inventors: Yousung LEE, Dongil YANG, Hyoseok NA, Doohwan LEE
  • Publication number: 20220191571
    Abstract: There is provided a device for providing personalized advertisements, the device including: a communicator; a personalized playlist processor configured to perform: (a) receiving a playlist of content from a system for providing the content through streaming; and (b) generating a personalized playlist including a uniform resource identifier (URI) of personalized advertising content based on the playlist; a content processor configured to receive the content and the personalized advertising content through the communicator using the personalized playlist, perform signal processing on the content and the personalized advertising content, and provide the content and the personalized advertising content; and a controller configured to control operations of the communicator, the personalized playlist processor, and the content processor.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 16, 2022
    Applicant: ANYPOINT MEDIA CO., LTD.
    Inventors: Wonjang BAEK, Doohwan LEE
  • Publication number: 20220181303
    Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 9, 2022
    Inventors: DOOHWAN LEE, JUNGSOO BYUN
  • Patent number: 11355445
    Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonsung Kim, Doohwan Lee, Taeho Ko, Bongsoo Kim, Seokbong Park
  • Patent number: 11342239
    Abstract: The invention provides a semiconductor package, which may include a connection structure including one or more redistribution layers. A semiconductor chip is disposed on the connection structure and has an active surface on which a connection pad electrically connected to the redistribution layer is disposed and an inactive surface opposite to the active surface. An encapsulant is disposed on the connection structure and covers at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant such that one exposed surface of the conductor pattern layer is exposed from the encapsulant. A metal layer is disposed on the encapsulant and covers the one exposed surface of the conductor pattern layer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunghawn Bae, Doohwan Lee, Jooyoung Choi
  • Patent number: 11323165
    Abstract: A wireless communication device includes a plurality of antenna elements; a modulation unit modulating signals including data in a plurality of first OAM modes having different real number values; a calculation unit calculating factors indicating weights corresponding to each of the signals in the plurality of first OAM modes modulated by the modulation unit for each of the plurality of antenna elements, based on information indicating a wireless environment of a counter wireless communication device that is a transmission destination of the data; and a transmission processing unit multiplexing each of the signals in the plurality of first OAM modes for each of the plurality of antenna elements by using the factors, and outputting the signals obtained through multiplexing for each of the plurality of antenna elements to each of the plurality of antenna elements.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 3, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Hirofumi Sasaki, Hiroyuki Fukumoto, Doohwan Lee, Hiroyuki Shiba
  • Patent number: 11302572
    Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: April 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dowan Kim, Doohwan Lee, Seunghwan Baek
  • Patent number: 11289456
    Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doohwan Lee, Jungsoo Byun
  • Publication number: 20220077078
    Abstract: A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm3.
    Type: Application
    Filed: April 27, 2021
    Publication date: March 10, 2022
    Inventors: Taesung Jeong, Doohwan Lee, Hongwon Kim, Junggon Choi
  • Patent number: 11228363
    Abstract: A transmitting station includes a plurality of transmitting weight multiplication units multiplying each of the transmission signal sequences by a transmitting weight, to be converted into MTX signals corresponding to UCAs forming an M-UCA so as to output the converted signals, and MTX transmitting OAM mode generation units inputting the signals corresponding to the UCAs and performing DFT on the input signals, so as to output to the corresponding UCA; and a receiving station includes MRX receiving OAM mode demultiplex units inputting signals from each of the UCAs forming the M-UCA and performing IDFT on the input signals, so as to output by each of received signal sequences, and a plurality of receiving weight multiplication units multiplying for each of them by a receiving weight, so as to demultiplex the spatially multiplexed received signal sequences and to output them in which interference between spatially multiplexed OAM modes is suppressed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 18, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Hirofumi Sasaki, Hiroyuki Fukumoto, Doohwan Lee, Hiroyuki Shiba
  • Publication number: 20210407962
    Abstract: A semiconductor package includes a base substrate, an interposer package disposed on the base substrate, and first and second semiconductor chips disposed on the interposer package, the interposer package includes a first redistribution layer, a bridge chip including a bridge circuit, and a vertical connection structure including a plurality of wiring layers, and wherein each of the first semiconductor chip and the second semiconductor chip is electrically connected to the bridge circuit and the plurality of wiring layers through the first redistribution layer.
    Type: Application
    Filed: January 21, 2021
    Publication date: December 30, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hongwon KIM, Junmo KOO, Yeonjoo KIM, Yunhee KIM, Jongkook KIM, Doohwan LEE, Jeongho LEE
  • Publication number: 20210407924
    Abstract: A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.
    Type: Application
    Filed: May 3, 2021
    Publication date: December 30, 2021
    Inventors: Jeongho LEE, Doohwan LEE