Abstract: A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.

Abstract: A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.

Abstract: A programming method includes a first program loop applying first and second pulses to a selected word line and thereafter determining a threshold voltage for the selected memory cell in relation to first and second verification voltages. Then, upon determining that the threshold voltage is lower than the first verification voltage, performing the second program loop by applying the first pulse to the selected word line, or upon determining that the threshold voltage is higher than the first verification voltage and lower than the second verification voltage, performing the second program loop by applying the second pulse to the selected word line.

Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

Abstract: Provided is a filtering apparatus, method, and medium for a multi-format codec, in which a blocking artifact of decoded video data is removed. The filtering apparatus includes a compression format detection unit, a block strength determination unit, a table determination unit, and a first filtering unit. The compression format detection unit detects a video compression format of the decoded video data. The block strength determination unit determines a block strength indicating a filtering strength with respect to the decoded video data according to the detected video compression format. The table determination unit determines a filtering table differently according to the block strength when the block strength is greater than a predetermined threshold. The first filtering unit performs filtering on the decoded video data in units of a block using the determined filtering table.

Abstract: According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.

Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

Abstract: A programming method includes a first program loop applying first and second pulses to a selected word line and thereafter determining a threshold voltage for the selected memory cell in relation to first and second verification voltages. Then, upon determining that the threshold voltage is lower than the first verification voltage, performing the second program loop by applying the first pulse to the selected word line, or upon determining that the threshold voltage is higher than the first verification voltage and lower than the second verification voltage, performing the second program loop by applying the second pulse to the selected word line.

Abstract: A dryer having a waste heat recovery device includes a cabinet, a drum rotatably mounted within the cabinet and having a front surface and a rear surface, an intake duct configured to provide an intake flow path through which air flows into the drum, an exhaust duct configured to exhaust air coming from the drum out of the cabinet, a heater configured to heat air flowing into the drum, and an ambient air duct configured to inhale air from outside the cabinet and supply the air from outside the cabinet into the drum. The waste heat recovery device includes an evaporation unit configured to absorb heat from air that is exhausted from the drum, a condenser unit configured to transfer heat absorbed from the evaporation unit to ambient air that flows into the ambient air duct, and a heat transfer medium configured to transfer heat between the evaporation unit and the condenser unit.

Abstract: A method, medium, and system encoding/decoding video data using a binary arithmetic coding adaptive to a compression bit rate of the video data. The system may include a bitrate adaptation unit determining a maximum length of a prefix using a compression bitrate of the video data, a binarization unit dividing the video data into a prefix and a suffix according to the determined maximum length of the prefix and binarizing the video data, and an arithmetic encoding unit performing an arithmetic encoding on the binarized video data. The video data may be encoded/decoded using binary arithmetic encoding/decoding by determining the maximum length of the prefix, an order of an exponential Golomb code, and the number of contexts based on the compression bitrate. Accordingly, it is possible to obtain high encoding efficiency regardless of a range of the desired compression bitrate.

Abstract: A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.

Abstract: A memory mapping apparatus and a method in a video decoder/encoder utilize a dividing unit, a storage unit and a memory allocation unit. The dividing unit divides picture data into macroblocks and divides each of the macroblocks, which are units of encoding, into partitions having a predetermined size. A storage unit comprises at least one memory bank which is independently accessible. A memory allocation unit allocates adjacent partitions to different memory banks. Accordingly, a total number of cycles necessary to read and write the picture data is reduced.

Abstract: An apparatus and method for writing and/or reading data in an image processing system are provided. The apparatus for writing data includes: a memory formed with at least one or more banks capable of being accessed independently; and a memory control unit controlling so that a luminance component, a first chrominance component and a second chrominance component belonging to one macroblock are written based on respective structures different to each other, in the memory. The apparatus for reading data includes: a memory formed with one or more banks capable of being accessed independently in which a luminance component, a first chrominance component, and a second chrominance component belonging to one macroblock are written based on respective structures different to each other, in each bank of the memory; and a memory control unit controlling so that a luminance component, a first chrominance component, and a second chrominance component required are read from the memory.

Abstract: Provided is an apparatus, medium, and method for processing neighbor information in a video decoder that can minimize the number of memory accesses. The apparatus includes a neighbor information providing unit and a storage unit. If at least one spatially neighboring block of a current block exists in memory, the neighbor information providing unit can access information of all neighbor blocks from the memory and provides the accessed information as neighbor information. The storage unit stores the neighbor information provided by the neighbor information providing unit and outputs the stored neighbor information to the plurality of modules.

Abstract: The disclosure describes an image encoding apparatus, method, and medium and an image decoding apparatus, method, and medium to encode and decode an original image. The disclosure also describes a display driving circuit and a method and medium using the same. The image encoding apparatus may include an encoding mode determiner that determines a first encoding mode and a second encoding mode to be encoding modes of a first pixel and a second pixel that are adjacent to each other and are included in a line, a first encoder that encodes the first pixel whose encoding mode is determined to be the first encoding mode to generate a first bitstream, and a second encoder that encodes a difference of the second pixel whose encoding mode is determined to be the second encoding mode from its reference pixel to generate a second bitstream.

Abstract: A display driving apparatus and method using a display device, such as a liquid crystal display device, and a medium for implementing a method of display driving method are provided. The display driving apparatus includes: an encoding unit which compresses and encodes image data to be displayed by the display device; a memory which stores the encoded image data; a memory control unit which stores the encoded image data in the memory and reads the encoded image data from the memory; and a decoding unit which decodes the encoded image data read out from the memory to restore the image data. Input image data is compressed and encoded in units of blocks, and the encoded image data is stored in a memory. Thereafter, the encoded image data stored in the memory is decoded, and the decoded result is output to a display device. Thus, it is possible to reduce the size of a memory included in a display driving apparatus without deteriorating the quality of an image displayed.

Abstract: A transforming and/or inverse transforming system, medium, and method for a multi-codec. The transforming system includes a first matrix storage storing 1-dimensional DCT (discrete cosine transform) matrixes corresponding to respective transformation techniques, a second matrix storage storing 2-dimensional DCT matrixes corresponding to the respective transformation techniques, a 1-dimensional transformer 1-dimensionally transforming an input image using a 1-dimensional DCT matrix corresponding to a set transformation technique, a 2-dimensional transformer 2-dimensionally transforming the 1-dimensionally transformed image using a 2-dimensional DCT matrix corresponding to a set transformation technique, and an enhancement transformer enhancement transforming the 1-dimensionally transformed image to improve efficiency of integer transformation.

Abstract: An image encoding apparatus and method, and an image decoding apparatus and method. An image encoding apparatus includes: an image input unit receiving an image to be encoded; a transform encoding unit transform coding the image provided from the image input unit to generate a first bitstream; a pulse code modulation (PCM) encoding unit PCM coding the image provided from the image input unit to generate a second bitstream; and a selector selecting and outputting one of the first bitstream and the second bitstream depending on characteristics of the image.

Abstract: A pipelining decoding apparatus and method, and a computer-readable recording medium for storing a computer program for controlling the pipelining decoding apparatus. Pixel values of each of the recovered images corresponding to previous macroblocks are stored as neighboring pixel values. Motion is predicted in a picture corresponding to a current macro block using the stored neighboring pixel values. An original image is recovered from the current macroblock using the result of the prediction of the motion in the picture and residue information. Some of the pixel values of the recovered image corresponding to the current macroblock are stored and the recovered image is deblocking-filtered.

Abstract: Provided are an image encoding apparatus, method, and medium; an image decoding apparatus, method, and medium; and a display driving circuit and method and apparatus using the same. The image encoding apparatus includes an encoding mode determiner that determines a first encoding mode and a second encoding mode to be encoding modes of a first pixel and a second pixel that are adjacent to each other and are included in a line, a first encoder that encodes the first pixel whose encoding mode is determined to be the first encoding mode to generate a first bitstream, and a second encoder that encodes a difference of the second pixel whose encoding mode is determined to be the second encoding mode from its reference pixel to generate a second bitstream.