Patents by Inventor Dorit Shapira
Dorit Shapira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230063955Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.Type: ApplicationFiled: October 21, 2022Publication date: March 2, 2023Inventors: DORON RAJWAN, EFRAIM ROTEM, ELIEZER WEISSMANN, AVINASH N. ANANTHAKRISHNAN, DORIT SHAPIRA
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Patent number: 11567556Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).Type: GrantFiled: March 27, 2020Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Chris Macnamara, John J. Browne, Tomasz Kantecki, David Hunt, Anatoly Burakov, Srihari Makineni, Nikhil Gupta, Ankush Varma, Dorit Shapira, Vasudevan Srinivasan, Bryan T. Butters, Shrikant M. Shah
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Patent number: 11481013Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.Type: GrantFiled: May 21, 2020Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Avinash N. Ananthakrishnan, Dorit Shapira
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Publication number: 20220100247Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.Type: ApplicationFiled: September 26, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Vivek Garg, Ankush Varma, Krishnakanth Sistla, Nikhil Gupta, Nikethan Shivanand Baligar, Stephen Wang, Nilanjan Palit, Timothy Kam, Adwait Purandare, Ujjwal Gupta, Stanley Chen, Dorit Shapira, Shruthi Venugopal, Suresh Chemudupati, Rupal Parikh, Eric Dehaemer, Pavithra Sampath, Phani Kumar Kandula, Yogesh Bansal, Dean Mulla, Michael Tulanowski, Stephen Haake, Andrew Herdrich, Ripan Das
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Publication number: 20210318742Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.Type: ApplicationFiled: June 22, 2021Publication date: October 14, 2021Applicant: Intel CorporationInventors: Dorit Shapira, Anand Enamandram, Daniel Cartagena, Krishnakanth Sistla, Jorge P. Rodriguez, Efraim Rotem, Nir Rosenzweig
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Patent number: 11144085Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.Type: GrantFiled: June 23, 2017Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Asma H. Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Dorit Shapira, Krishnakanth Sistla, Nikhil Gupta, Vasudevan Srinivasan, Chris MacNamara
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Patent number: 11054877Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.Type: GrantFiled: June 19, 2018Date of Patent: July 6, 2021Assignee: Intel CorporationInventors: Dorit Shapira, Anand K. Enamandram, Daniel Cartagena, Krishnakanth Sistla, Jorge P. Rodriguez, Efraim Rotem, Nir Rosenzweig
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Publication number: 20210191490Abstract: Methods and apparatus for balancing power between discrete components, such as processing units (e.g., CPUs) and accelerators in a compute node or platform. Power consumption of the compute platform is monitored to detect for conditions under which a threshold (e.g., power supply capacity threshold) is exceeded. In response, the operating frequencies of a processing unit and/or other platform components such as accelerators, are adjusted to reduce the power consumption of the platform to return below the threshold. Power limit biasing hints (scaling weights) are provided to platform components, along with a power violation index, which are used to adjust the operating frequencies of the platform components. Optionally, a processing unit can calculate the power violation index and the scaling weights and directly control the frequencies of itself and platform components. Embodiments of multi-socket platforms are also provided.Type: ApplicationFiled: March 3, 2021Publication date: June 24, 2021Inventors: Phani Kumar KANDULA, Eric J. DEHAEMER, Dorit SHAPIRA, Ramkumar NAGAPPAN, Vivek GARG, Fuat KECELI, Mani PRAKASH, David C. HOLCOMB, Horthense D. TAMDEM, Olivier FRANZA, Vjekoslav SVILAN
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Patent number: 11029744Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.Type: GrantFiled: December 29, 2017Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Efraim Rotem, Esfir Natanzon, Doron Rajwan, Eliezer Weissmann, Dorit Shapira, Lily P. Looi, Bart Plackle, Nadav Shulman
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Patent number: 11016916Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.Type: GrantFiled: May 7, 2020Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Xiuting C. Man, Jeremy J. Shrall, Deepak Ganapathy, Dorit Shapira
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Publication number: 20200285294Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.Type: ApplicationFiled: May 21, 2020Publication date: September 10, 2020Inventors: DORON RAJWAN, EFRAIM ROTEM, ELIEZER WEISSMANN, AVINASH N. ANANTHAKRISHNAN, DORIT SHAPIRA
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Publication number: 20200264996Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.Type: ApplicationFiled: May 7, 2020Publication date: August 20, 2020Inventors: XIUTING C. MAN, JEREMY J. SHRALL, DEEPAK GANAPATHY, DORIT SHAPIRA
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Publication number: 20200225724Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Chris MACNAMARA, John J. BROWNE, Tomasz KANTECKI, David HUNT, Anatoly BURAKOV, Srihari MAKINENI, Nikhil GUPTA, Ankush VARMA, Dorit SHAPIRA, Vasudevan SRINIVASAN, Bryan T. BUTTERS, Shrikant M. SHAH
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Patent number: 10678319Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.Type: GrantFiled: January 18, 2019Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Avinash N. Ananthakrishnan, Dorit Shapira
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Patent number: 10657083Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.Type: GrantFiled: September 30, 2016Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Xiuting C. Man, Jeremy J. Shrall, Deepak Ganapathy, Dorit Shapira
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Patent number: 10474216Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.Type: GrantFiled: December 16, 2015Date of Patent: November 12, 2019Assignee: INTEL CORPORATIONInventors: Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim (Efi) Rotem, Tal Kuzi, Eliezer Weissmann, Tomer Ziv, Nir Rosenzweig
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Publication number: 20190204893Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Inventors: Efraim Rotem, Esfir Natanzon, Doron Rajwan, Eliezer Weissmann, Dorit Shapira, Lily P. Looi, Bart Plackle, Nadav Shulman
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Publication number: 20190155362Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.Type: ApplicationFiled: January 18, 2019Publication date: May 23, 2019Inventors: Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Avinash N. Ananthakrishnan, Dorit Shapira
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Patent number: 10289514Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.Type: GrantFiled: June 30, 2014Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Eric Distefano, James G. Hermerding, II, Esfir Natanzon
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Patent number: 10216246Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.Type: GrantFiled: September 30, 2016Date of Patent: February 26, 2019Assignee: Intel CorporationInventors: Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Avinash N. Ananthakrishnan, Dorit Shapira