Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.

Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes at least one execution unit to execute instructions, and an interrupt generation unit. The interrupt generation unit may be to: receive a plurality of values indicating thermal status values for a memory unit at multiple points in time across a first time window; determine a running average value based on the plurality of values indicating thermal status values in the memory unit; and in response to a determination that the running average value has exceeded a high thermal status threshold value, generate a thermal interrupt indicating a high thermal status event in the processor. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.

Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.

Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.

Abstract: In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.