Abstract: Systems, methods, and devices that perform computing operations are provided. In one example, a system includes a least one node, the at least one node having one or more processors, each having associated memory, a clock, a scheduler, the scheduler monitoring one or more of rates, rates of lanes, rates at which packets are sent, times, latencies of packets, topology, communication states, nodes, and packets in the system, an attribute monitor that measures counters for one or more of congestion state, line rate, and communication attributes. A packet scheduler determines a destination node based on information from the scheduler and the attribute monitor, and sends at least a portion of a packet to the destination node.

Abstract: In one embodiment, a responder device is associated with a data communication bus between a host device and a peripheral device, the host device being to execute a virtual machine (VM) and maintain a master clock time, the peripheral device being to execute a virtual function (VF) associated with the VM, and the responder device includes an interface to share data with the peripheral device, and processing circuitry to transform values of the master clock time to a frame of reference of the VM based on a transformation between the master clock time and a virtual counter value of the VM, and perform a time measurement dialogue with the VF including measurement messages exchanged by the responder device and the peripheral device, the measurement messages including translated values of the master clock time in the frame of reference of the VM.

Abstract: In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

Abstract: Approaches presented herein provide for the isolation of electronic components, such as oscillators, that may be sensitive to environmental conditions such as temperature. In at least one embodiment, an isolation assembly can be provided that includes a sealed housing for preventing ambient air from reaching an oscillator operating within an inner chamber of the sealed housing. The walls of the inner chamber can have a layer of low-emissivity blocking material that can reduce the amount of heat transferred to the oscillator due to radiation. The inner chamber can also be connected to a vacuum through an air valve that allows the pressure in the chamber to be reduced, to reduce an amount of heat transfer due to conduction.

Abstract: Aspects of the present disclosure are directed to systems, methods, and computer readable media for dynamic data transfer rate control. One method includes alternating a network device between a plurality of supported data transfer rates that are supported by the network device to achieve an unsupported data transfer rate that is not supported by the network device. Another method includes adding one or more dummy work descriptors to a data stream, and transmitting the data stream including the one or more dummy work descriptors at a supported data transfer rate that is supported by a network device to achieve an effective unsupported data transfer rate that is not supported by the network device.

Abstract: A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

Abstract: A system for video encoding includes an acceleration device to select from a video stream a plurality of target video frames and one or more reference frames, to divide each of the target video frames into multiple blocks, and to compute at least a first map, including respective first motion vectors between the blocks in the a target video frame and corresponding blocks in one of the reference frames, and a second map, including respective second motion vectors between the blocks in a second target video frame and corresponding blocks in the one of the reference frames. A control unit is to encode one of the first and second target video frames based on the one of the reference frames by selecting motion vectors from among the first motion vectors in the first map or the second motion vectors in the second map.

Abstract: In one embodiment, a device includes clock circuitry including an oscillator to generate a local clock signal having a clock frequency, and a hardware clock to maintain a local clock responsively to the clock signal, at least one sensor to measure at least one value of at least one environmental parameter, processing circuitry to find at least one value of at least one filter parameter based on the at least one value of the at least one environmental parameter, and a filter to receive an error signal between a remote clock and the local clock, and filter the error signal and generate an adjustment to cause the clock circuitry to adjust the local clock signal or the local clock based on the at least one value of the at least one filter parameter.

Abstract: Systems and methods herein are for a video encoder to be associated with a rate optimization distortion (RDO) module and a calibration module, where the RDO module may be to perform RDO for received frames of a media stream and may be to generate at least an RDO output that is based in part on quality measures between the received frames and decoded frames, and where the calibration module may be to provide an evaluation metric that is to scale or transform at least a range of the quality measures, with the scaling or transforming to potentially reduce an effect on a compression performed in the video encoder.

Abstract: Systems and methods herein are for a video encoder to be associated with a temporal filter and a coding tree and that can perform a main pass for video encoding using individual video blocks towards prediction of at least one frame associated with the media stream, where the coding tree is associated with a lookahead pass, and where the temporal filter can enable denoising within the lookahead pass to reduce an effect of noise in one or more of motion estimation or mode selection of the video encoding.

Abstract: A communication system includes a primary clock device having a precision clock and configured to transmit pulse signals at a constant rate. The communication system further includes a plurality of agent devices, each agent device comprising an internal timestamp control loop, a timestamp generator configured to update timestamps at an adjustable increment rate, and control logic configured to synchronize the agent device with the primary clock device using the internal timestamp control loop. The control logic enables each agent device to maintain synchronization with the primary clock device by adjusting the adjustable increment rate based on timing differences between estimated and actual signal reception times.

Abstract: Systems, methods, and devices that perform computing operations are provided. In one example, a system includes a least one node, the at least one node having one or more processors, each having associated memory, a clock, a scheduler, the scheduler monitoring one or more of rates, rates of lanes, rates at which packets are sent, times, latencies of packets, topology, communication states, nodes, and packets in the system, an attribute monitor that measures counters for one or more of congestion state, line rate, and communication attributes. A packet scheduler determines a destination node based on information from the scheduler and the attribute monitor, and sends at least a portion of a packet to the destination node.

Abstract: A system including a device, coupled to a link and including a transmitter, generates a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device interleaves the control block between two of a plurality of data blocks of a data packet, and transmits, via the link, the data packet and the control block.

Abstract: Approaches presented herein provide for the isolation of electronic components, such as oscillators, that may be sensitive to environmental conditions such as temperature. In at least one embodiment, an isolation assembly can be provided that includes a sealed housing for preventing ambient air from reaching an oscillator operating within an inner chamber of the sealed housing. The walls of the inner chamber can have a layer of low-emissivity blocking material that can reduce the amount of heat transferred to the oscillator due to radiation. The inner chamber can also be connected to a vacuum through an air valve that allows the pressure in the chamber to be reduced, to reduce an amount of heat transfer due to conduction.

Abstract: A device includes a receiver including a timestamp generator to update timestamps at a first rate. The receiver is to estimate a first time for receiving a signal, wherein the signal is associated with a synchronization operation. The receiver is further to receive the signal at a second time. The receiver is further to determine a difference between the second time and the first time, wherein the difference is associated with an error of the timestamp generator of the receiver. The receiver can also adjust the first rate to a second rate at which to update the timestamps by the timestamp generator, responsive to determining the difference between the first time and the second time.

Abstract: Systems and methods herein are for distributed image processing by at least a data processing unit (DPU) and using at least a graphics processing unit (GPU) in possible association with a field programmable gate array (FPGA). For example, the FPGA may be used to perform physical layer processing for images captured by the image sensor or from a simulation and can provide a media stream for the DPU and the DPU can provide payload of only image sections from the images in a media stream for the GPU to perform content layer processing for only the image sections of the images.

Abstract: Systems and methods herein are for image-based defect detection for items moving through a manufacturing area. A data processing unit (DPU) is in communication with multiple graphics processing units (GPUs) and can receive images captured of an item, as well as receive an indication of image sections of the images associated with a characteristic of a manufacturing process of the item. The DPU can provide the image sections to the GPUs for image processing to determine a value associated with the characteristic of the manufacturing process of the item. The provision of the image sections may be based at least in part on the individual ones of the GPUs being associated with a feature of the item, and the GPUs can perform different image processing based at least in part on different features of the items.

Abstract: Systems and methods herein are for distributed image processing by at least a data processing unit (DPU) and using at least a graphics processing unit (GPU) in possible association with a field programmable gate array (FPGA). For example, the FPGA may be used to perform physical layer processing for images captured by the image sensor or from a simulation and can provide a media stream for the DPU and the DPU can provide payload of only image sections from the images in a media stream for the GPU to perform content layer processing for only the image sections of the images.

Abstract: In one embodiment, a system includes a peripheral data connection bus configured to connect to devices and transfer data between the devices, a scheduling machine configured to connect to the peripheral data connection bus and send a read request message to a first processing device, and the first processing device configured to be connected to the peripheral data connection bus, and responsively to the read request message add a time value to a read response message, and provide the read response message to the scheduling machine, and wherein the scheduling machine is configured to read the time value from the provided read response message and schedule processing of an operation by a second processing device responsively to the read time value.

Abstract: A network adapter comprises an output that couples to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to be synchronized with a second clock that is external to the CPU and the network adapter, and circuitry coupled to the first clock. The circuitry is configured to generate, using the synchronized first clock, a tick at a time offset from a timeslot of a radio schedule for a radio unit and send the tick to the output.