Abstract: Embodiments of the present disclosure are directed to synchronizing clocks across a plurality of computing devices. Generally speaking, the clocks of the plurality of devices can be synchronized to whichever of the clocks is the furthest ahead in time. More specifically, embodiments provide for determining a common time reference establishment without need for an external reference. Rather, a computing device or node with the furthest ahead in time clock among devices or nodes in a group or time domain can be become the leader node and propagate time to the other nodes. Embodiments of the present disclosure can replace the traditional one-way time transfer from the IEEE 1588 timeTransmitter to the timeReceiver with two-way communication and time transfer.

Abstract: In one embodiment, a system, includes a digitally controlled oscillator (DCO) to generate a local clock signal having a local clock frequency, and a hardware clock to maintain a value indicative of a local clock time advancing at a frequency proportional to the local clock frequency of the local clock signal generated by the DCO, and clock synchronization circuitry to receive from a device an indication of a remote clock time, generate a digital control command to at least partially correct for a difference between the remote clock time and the local clock time, and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

Abstract: Systems and methods herein are for a video encoder to be associated with a rate optimization distortion (RDO) module and a calibration module, where the RDO module may be to perform RDO for received frames of a media stream and may be to generate at least an RDO output that is based in part on quality measures between the received frames and decoded frames, and where the calibration module may be to provide an evaluation metric that is to scale or transform at least a range of the quality measures, with the scaling or transforming to potentially reduce an effect on a compression performed in the video encoder.

Abstract: A network device includes control logic coupled to a receiver. The network device receives, via the receiver, a packet from a second network device over a network, wherein the packet is associated with clock synchronization between the network device and the second network device. The network device determines that a congestion indicator of the packet is asserted, indicating that the packet has incurred congestion traversing the network and adjust, based on an assertion of the congestion indicator, a weight applied to timestamps associated with the packet in performing clock synchronization with the second network device.

Abstract: In one embodiment, a peripheral device includes an oscillator, a counter driven by the oscillator providing a peripheral device counter value, and processing circuitry to receive host device counter values from multiple host devices, read host device clock translation parameters from host memories providing translation between host device counter values and host device clock times, read peripheral device clock translation parameters providing translation between the peripheral device counter value and one or more peripheral device clock times, compute clock corrections, and correct the peripheral device clock translation parameters, or correct the host device clock translation parameters.

Abstract: A system includes a device coupled to a processing device. The processing device is to receive a timing signal associated with a synchronized time. The processing device is further to synchronize a rate limiter of the device to the synchronized time responsive to receiving the timing signal, wherein the rate limiter is configured to schedule one or more workloads at a respective rate. The processing device is to receive a request to execute the one or more workloads, the request comprising a rate to execute each workload of the one or more workloads. The processing device is to execute the one or more workloads at the respective rate upon synchronizing the rate limiter.

Abstract: Methods and systems for obtaining data having a first format, converting the data to a second format, storing the converted data in memory accessible by at least one parallel processing unit, and processing the converted data stored in the memory using the at least one parallel processing unit.

Abstract: In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.

Abstract: A system for video encoding includes an acceleration device, to select from a video stream a target video frame and one or more reference frames. The target and reference frames are divided into respective first pluralities of first blocks of a first size and into respective second pluralities of second blocks of a second size, larger than the first size. At least a first map and a second map are computed, including respective motion vectors between each first block in the target video frame and corresponding first blocks in the reference frames, and between each second block in the target video frame and corresponding second blocks in the one or more reference frames. A control unit encodes the target video frame based on at least one of the reference frames by selecting motion vectors from among the motion vectors in the first and second maps.

Abstract: In one embodiment, a pluggable clock module apparatus includes a module housing, a physical interface to be plugged into a network port of a network device, and an oscillator disposed in the module housing, the oscillator being to generate a clock signal. In another embodiment, a system includes a network device including network ports and a pluggable clock module apparatus including a physical interface to be plugged into one of the network ports. The pluggable clock module apparatus is to provide the clock signal, or a network signal based on the clock signal, to the network device. The network device is to receive the clock signal, or recover the clock from the network signal, and to provide the clock signal to other devices in a network.

Abstract: Systems, methods, and devices that perform computing operations are provided. In one example, a system includes a least one node, the at least one node having one or more processors, each having associated memory, a clock, a scheduler, the scheduler monitoring one or more of rates, rates of lanes, rates at which packets are sent, times, latencies of packets, topology, communication states, nodes, and packets in the system, an attribute monitor that measures counters for one or more of congestion state, line rate, and communication attributes. A packet scheduler determines a destination node based on information from the scheduler and the attribute monitor, and sends at least a portion of a packet to the destination node.

Abstract: In one embodiment, a responder device is associated with a data communication bus between a host device and a peripheral device, the host device being to execute a virtual machine (VM) and maintain a master clock time, the peripheral device being to execute a virtual function (VF) associated with the VM, and the responder device includes an interface to share data with the peripheral device, and processing circuitry to transform values of the master clock time to a frame of reference of the VM based on a transformation between the master clock time and a virtual counter value of the VM, and perform a time measurement dialogue with the VF including measurement messages exchanged by the responder device and the peripheral device, the measurement messages including translated values of the master clock time in the frame of reference of the VM.

Abstract: In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

Abstract: Approaches presented herein provide for the isolation of electronic components, such as oscillators, that may be sensitive to environmental conditions such as temperature. In at least one embodiment, an isolation assembly can be provided that includes a sealed housing for preventing ambient air from reaching an oscillator operating within an inner chamber of the sealed housing. The walls of the inner chamber can have a layer of low-emissivity blocking material that can reduce the amount of heat transferred to the oscillator due to radiation. The inner chamber can also be connected to a vacuum through an air valve that allows the pressure in the chamber to be reduced, to reduce an amount of heat transfer due to conduction.

Abstract: Aspects of the present disclosure are directed to systems, methods, and computer readable media for dynamic data transfer rate control. One method includes alternating a network device between a plurality of supported data transfer rates that are supported by the network device to achieve an unsupported data transfer rate that is not supported by the network device. Another method includes adding one or more dummy work descriptors to a data stream, and transmitting the data stream including the one or more dummy work descriptors at a supported data transfer rate that is supported by a network device to achieve an effective unsupported data transfer rate that is not supported by the network device.

Abstract: A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

Abstract: A system for video encoding includes an acceleration device to select from a video stream a plurality of target video frames and one or more reference frames, to divide each of the target video frames into multiple blocks, and to compute at least a first map, including respective first motion vectors between the blocks in the a target video frame and corresponding blocks in one of the reference frames, and a second map, including respective second motion vectors between the blocks in a second target video frame and corresponding blocks in the one of the reference frames. A control unit is to encode one of the first and second target video frames based on the one of the reference frames by selecting motion vectors from among the first motion vectors in the first map or the second motion vectors in the second map.

Abstract: In one embodiment, a device includes clock circuitry including an oscillator to generate a local clock signal having a clock frequency, and a hardware clock to maintain a local clock responsively to the clock signal, at least one sensor to measure at least one value of at least one environmental parameter, processing circuitry to find at least one value of at least one filter parameter based on the at least one value of the at least one environmental parameter, and a filter to receive an error signal between a remote clock and the local clock, and filter the error signal and generate an adjustment to cause the clock circuitry to adjust the local clock signal or the local clock based on the at least one value of the at least one filter parameter.

Abstract: Systems and methods herein are for a video encoder to be associated with a rate optimization distortion (RDO) module and a calibration module, where the RDO module may be to perform RDO for received frames of a media stream and may be to generate at least an RDO output that is based in part on quality measures between the received frames and decoded frames, and where the calibration module may be to provide an evaluation metric that is to scale or transform at least a range of the quality measures, with the scaling or transforming to potentially reduce an effect on a compression performed in the video encoder.

Abstract: Systems and methods herein are for a video encoder to be associated with a temporal filter and a coding tree and that can perform a main pass for video encoding using individual video blocks towards prediction of at least one frame associated with the media stream, where the coding tree is associated with a lookahead pass, and where the temporal filter can enable denoising within the lookahead pass to reduce an effect of noise in one or more of motion estimation or mode selection of the video encoding.