Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit. In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: A processing core using a lock scoreboard mechanism is provided. The lock scoreboard is adapted to manage a load-lock instruction. The load-lock scoreboard includes a plurality of scoreboard entries representing different conditions that must be met before the load-lock instruction can be retired. During execution of the load-lock instruction retirement conditions are speculatively performed, and the scoreboard is updated and checked accordingly. If the scoreboard indicates that one or more retirement conditions are not met, the load-lock instruction is replayed. Otherwise, the load-lock instruction is permitted to retire. Scoreboard management functions routinely update scoreboard contents as retirement conditions are cleared. This enables rapid retirement of load-lock operations.

Abstract: A processing core using a lock scoreboard mechanism is provided. The lock scoreboard is adapted to manage a load-lock instruction. The load-lock scoreboard includes a plurality of scoreboard entries representing different conditions that must be met before the load-lock instruction can be retired. During execution of the load-lock instruction retirement conditions are speculatively performed, and the scoreboard is updated and checked accordingly. If the scoreboard indicates that one or more retirement conditions are not met, the load-lock instruction is replayed. Otherwise, the load-lock instruction is permitted to retire. Scoreboard management functions routinely update scoreboard contents as retirement conditions are cleared. This enables rapid retirement of load-lock operations.

Abstract: A processing core using a lock scoreboard mechanism is provided. The lock scoreboard is adapted to manage a load-lock instruction. The load-lock scoreboard includes a plurality of scoreboard entries representing different conditions that must be met before the load-lock instruction can be retired. During execution of the load-lock instruction retirement conditions are speculatively performed, and the scoreboard is updated and checked accordingly. If the scoreboard indicates that one or more retirement conditions are not met, the load-lock instruction is replayed. Otherwise, the load-lock instruction is permitted to retire. Scoreboard management functions routinely update scoreboard contents as retirement conditions are cleared. This enables rapid retirement of load-lock operations.