Patents by Inventor Doug Ingerly

Doug Ingerly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200035560
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Application
    Filed: August 25, 2017
    Publication date: January 30, 2020
    Applicant: Intel Corporation
    Inventors: Bruce BLOCK, Valluri R. RAO, Patrick MORROW, Rishabh MEHANDRU, Doug INGERLY, Kimin JUN, Kevin O'BRIEN, Patrick MORROW, Szyua S. LIAO
  • Patent number: 8154121
    Abstract: Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones having a first monomeric unit and a second monomeric unit wherein the first monomeric unit has a different chemical structure than the second monomeric unit and wherein the copolymer backbones are cross-linked by a first cross-linker or a second cross-linker, or combinations thereof.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Kunal Shah, Michael Haverty, Sadasivan Shankar, Doug Ingerly, Grant Kloster
  • Publication number: 20090212421
    Abstract: Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones having a first monomeric unit and a second monomeric unit wherein the first monomeric unit has a different chemical structure than the second monomeric unit and wherein the copolymer backbones are cross-linked by a first cross-linker or a second cross-linker, or combinations thereof.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventors: Kunal Shah, Michael Haverty, Sadasivan Shankar, Doug Ingerly, Grant Kloster