Abstract: An electronic device with a non-volatile memory includes a non-volatile memory (NVM) cell selectively programmable to change a program state from a first state to a second state or to a third state, and may also include a write circuit configured to selectively program the NVM cell to change the program state from the first state to the second state by applying a programming voltage signal to a first source/drain region and to change the program state from the first state to the third state by applying the programming voltage signal to a second source/drain region. A read circuit is configured to identify the program state of the NVM memory cell as one of the first state, the second state, and the third state based on a cell voltage of the non-volatile memory cell.

Abstract: The present disclosure generally relates to a buried channel semiconductor device that includes one or more energy barrier modulation regions. In an example, a device includes a source/drain region, an energy barrier modulation region, a channel covering surface region, and a gate structure. The source/drain region is in a doped region in a semiconductor substrate that has an upper surface. The energy barrier modulation and channel covering surface regions are in the doped region and at the upper surface. The gate structure is over the upper surface. The energy barrier modulation and channel covering surface regions underlie the gate structure. The energy barrier modulation region is laterally between the source/drain and channel covering surface regions. The doped and energy barrier modulation regions are doped with a first conductivity type, and the source/drain and channel covering surface regions are doped with a second conductivity type opposite from the first conductivity type.

Abstract: In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concentration than the dopant concentration in the second well.

Abstract: In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

Abstract: A method of forming an electronic device includes forming an opening through a dielectric layer located over a first resistive layer, the first resistive layer having a first sheet resistance. A second resistive layer is deposited over the dielectric layer and into the opening. The second resistive layer has a second sheet resistance different from the first sheet resistance. A portion of the second resistive layer is removed, thereby forming first and second noncontiguous portions of the second resistive layer, wherein the second portion of the second resistive layer contacts the first resistive layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concentration than the dopant concentration in the second well.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concertation than the dopant concentration in the second well.

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

Abstract: An electronic device, e.g. an integrated circuit, includes one or more test modules each having first and second pairs of contact pads arranged along a first axis, and a third pair of contact pads arranged along a second axis parallel to the first axis. A first connection bus connects contact pads in the first pair, a second connection bus connects contact pads in the second pair, and a third connection bus connects contact pads of the third pair. A first device under test (DUT) is connected between the first connection bus and the third connection bus, and a second DUT is connected between the second connection bus and the third connection bus.

Abstract: An electronic device, e.g. an integrated circuit, includes one or more test modules each having first and second pairs of contact pads arranged along a first axis, and a third pair of contact pads arranged along a second axis parallel to the first axis. A first connection bus connects contact pads in the first pair, a second connection bus connects contact pads in the second pair, and a third connection bus connects contact pads of the third pair. A first device under test (DUT) is connected between the first connection bus and the third connection bus, and a second DUT is connected between the second connection bus and the third connection bus.

Abstract: In one disclosed embodiment, a non-volatile memory cell is constructed using a floating gate transistor with a channel that includes a buried channel region interposed between two surface channel regions under a floating gate. The surface channel regions are formed using angled lightly-doped drain implantation at locations in the substrate so that a first surface channel region is located under a first end of the floating gate and a second surface channel region is located under a second end of the floating gate. In one embodiment, the floating gate transistor is a PMOS transistor, with the channel being formed in an n-well formed in a p-type substrate, with the buried channel region being formed using a Vtp implant, and with the surface channel regions being formed using angled NLDD implants. The surface channel regions increase the energy barrier along the channel and reduce off state current of the memory cell.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. First and second wells are located within the substrate, the first well being formed with a dopant of the first conductivity type, e.g. n-type, and the second well formed with a dopant of a second different conductivity type, e.g. p-type. A doped gap region is located between the first and second wells. The doped gap region is formed with a dopant of the second conductivity type, e.g. p-type, at a lower dopant concertation than the dopant concentration in the second well.

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

Abstract: In one disclosed embodiment, a non-volatile memory cell is constructed using a floating gate transistor with a channel that includes a buried channel region interposed between two surface channel regions under a floating gate. The surface channel regions are formed using angled lightly-doped drain implantation at locations in the substrate so that a first surface channel region is located under a first end of the floating gate and a second surface channel region is located under a second end of the floating gate. In one embodiment, the floating gate transistor is a PMOS transistor, with the channel being formed in an n-well formed in a p-type substrate, with the buried channel region being formed using a Vtp implant, and with the surface channel regions being formed using angled NLDD implants. The surface channel regions increase the energy barrier along the channel and reduce off state current of the memory cell.

Abstract: A method to integrate a vertical IMPATT diode in a planar process.

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

Abstract: An electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate and having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate and having a second sheet resistance that is different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.

Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.