Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

Abstract: A method to integrate a vertical IMPATT diode in a planar process.

Abstract: A method to integrate a vertical IMPATT diode in a planar process.

Abstract: A method to integrate a vertical IMPATT diode in a planar process.

Abstract: A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.

Abstract: A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.

Abstract: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.

Abstract: A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.