Patents by Inventor Douglas C. La Tulipe
Douglas C. La Tulipe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7666723Abstract: Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.Type: GrantFiled: February 22, 2007Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: David J. Frank, Douglas C. La Tulipe, Jr., Steven E. Steen, Anna W. Topol
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Publication number: 20100006972Abstract: An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: DOUGLAS C. LA TULIPE, JR., Sampath Purushothaman, James Vichiconti
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Patent number: 7528056Abstract: A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.Type: GrantFiled: January 12, 2007Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Meikei Ieong, Douglas C. La Tulipe, Jr., Leathen Shi, Anna W. Topol, James Vichiconti, Albert M. Young
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Publication number: 20090065941Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.Type: ApplicationFiled: September 11, 2007Publication date: March 12, 2009Inventors: Douglas C. La Tulipe, JR., Mark Todhunter Robson
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Publication number: 20090068835Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.Type: ApplicationFiled: September 11, 2007Publication date: March 12, 2009Inventors: Douglas C. La Tulipe, JR., Mark Todhunter Robson
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Patent number: 7494915Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: GrantFiled: August 9, 2006Date of Patent: February 24, 2009Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Erdem Kaltalioglu, Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Jochen Schacht, Andrew H. Simon, Terry A. Spooner, Yun-Yu Wang, Clement H. Wann, Chih-Chao Yang
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Patent number: 7488630Abstract: A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.Type: GrantFiled: March 6, 2007Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: David J. Frank, Douglas C. La Tulipe, Jr., Leathen Shi, Steven E. Steen, Anna W. Topol
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Publication number: 20080217782Abstract: A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.Type: ApplicationFiled: March 6, 2007Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David J. Frank, Douglas C. La Tulipe, Leathen Shi, Steven E. Steen, Anna W. Topol
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Publication number: 20080206977Abstract: Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.Type: ApplicationFiled: February 22, 2007Publication date: August 28, 2008Inventors: David J. Frank, Douglas C. La Tulipe, Steven E. Steen, Anna W. Topol
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Publication number: 20080203137Abstract: Bonding methods and a bonding system including monitoring are disclosed. In one embodiment, a method of monitoring bonding a first and second substrate includes: providing a plurality of piezoelectric sensors to a substrate mounting stage of a substrate bonding system; and monitoring a force change measured by the plurality of piezoelectric sensors induced by a bond front between the first and second substrate during bonding. This method allows real time monitoring of the bonding quality and adjustment of the bonding process parameters.Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Applicant: International Business Machines CorporationInventors: Douglas C. La Tulipe, Steven E. Steen, Anna W. Topol
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Publication number: 20080188036Abstract: A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.Type: ApplicationFiled: February 7, 2007Publication date: August 7, 2008Inventors: Douglas C. La Tulipe, Steven E. Steen, Anna W. Topol
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Publication number: 20080171423Abstract: A cost-effective and simple method of fabricating strained semiconductor-on-insulator (SSOI) structures which avoids epitaxial growth and subsequent wafer bonding processing steps is provided. In accordance with the present invention, a strain-memorization technique is used to create strained semiconductor regions on a SOI substrate. The transistors formed on the strained semiconductor regions have higher carrier mobility because the Si regions have been strained. The inventive method includes (i) ion implantation to create a thin amorphization layer, (ii) deposition of a high stress film on the amorphization layer, (iii) a thermal anneal to recrystallize the amorphization layer, and (iv) removal of the stress film. Because the SOI substrate was under stress during the recrystallization process, the final semiconductor layer will be under stress as well. The amount of stress and the polaity (tensile or compressive) of the stress can be controlled by the type and thickness of the stress films.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Meikei Ieong, Douglas C. La Tulipe, Leathen Shi, Anna W. Topol, James Vichiconti, Albert M. Young
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Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Patent number: 7241696Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.Type: GrantFiled: December 11, 2002Date of Patent: July 10, 2007Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Larry Clevenger, Timothy Joseph Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik Kumar, Douglas C. La Tulipe, Jr., Soon-Cheon Seo, Andrew Herbert Simon, Yun-Yu Wang, Chih-Chao Yang, Haining Yang -
Patent number: 7241681Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: GrantFiled: January 12, 2006Date of Patent: July 10, 2007Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
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Patent number: 7125792Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: GrantFiled: October 14, 2003Date of Patent: October 24, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Douglas C. La Tulipe, Timothy Dalton, Larry Clevenger, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht
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Patent number: 7122462Abstract: An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.Type: GrantFiled: November 21, 2003Date of Patent: October 17, 2006Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Erdem Kaltalioglu, Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Jochen Schacht, Andrew H. Simon, Terry A. Spooner, Yun-Yu Wang, Clement H. Wann, Chih-Chao Yang
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Patent number: 7091612Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: GrantFiled: October 14, 2003Date of Patent: August 15, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Timothy Dalton, Larry Clevenger, Andy Cowley, Douglas C. La Tulipe, Mark Hoinkis, Chih-Chao Yang, Yi-Hsiung Lin, Erdem Kaltalioglu, Markus Naujok, Jochen Schacht
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Patent number: 7052621Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: GrantFiled: June 13, 2003Date of Patent: May 30, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
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Patent number: 7001835Abstract: A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 ?Ohm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.Type: GrantFiled: November 21, 2003Date of Patent: February 21, 2006Assignees: International Business Machines Corporation, Infineon Technologies, AGInventors: Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik A. Kumar, Stephen M. Rossnagel, Andrew H. Simon, Douglas C. La Tulipe, Jr.
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Publication number: 20040251234Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: ApplicationFiled: June 13, 2003Publication date: December 16, 2004Inventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang