Patents by Inventor Douglas L. Sandy

Douglas L. Sandy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10327357
    Abstract: A canister system having a cylindrical housing and a modular electronic rack system disposed within the cylindrical housing. The modular electronic rack system includes a thermal contact member that is in at least selective physical contact with an interior surface of the cylindrical housing to permit conductive heat transfer there through. An input/output device extends along at least a portion of the modular electronic rack system and includes a power input and a signal output electrically coupled thereto. A plurality of electronic slots disposed at a position generally along the modular electronic rack system is provided.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 18, 2019
    Assignee: Artesyn Embedded Computing, Inc.
    Inventors: Martin Peter John Cornes, Suzanne Marye Wong, Ross L. Armstrong, Douglas L. Sandy
  • Patent number: 9439312
    Abstract: A canister system having a cylindrical housing, having at least one enclosed end, and a modular electronic rack system disposed within the cylindrical housing. The modular electronic rack system including an input/output device extending along at least a portion of the modular electronic rack system. The modular electronic rack system further having a power input and a signal output electrically coupled to the input/output device—at least one of the power input and the signal output extending through the at least one enclosed end of the cylindrical housing at a first sealed terminal. The canister system further having a first alignment system for physically aligning an electronic connection with the sealed terminal. The electronic connection having physically engaging features extending from the cylindrical housing to align the electronic connection therewith.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: September 6, 2016
    Assignee: Artesyn Embedded Computing, Inc.
    Inventors: Martin Peter John Cornes, Suzanne Marye Wong, Ross L. Armstrong, Douglas L. Sandy
  • Patent number: 9288929
    Abstract: A ruggedized canister system having a cylindrical housing and a modular electronic rack system disposed therein. The modular electronic rack system includes a backplane and a plurality of rib members radiating outwardly from the backplane. The rib members extend from the backplane at a proximal end in a direction generally orthogonal to the longitudinal axis of the backplane toward a distal end. An input/output device extends along at least a portion of the backplane and includes a power input and a signal output electrically coupled thereto. A plurality of electronic slots are positioned within a space define by the rib members when viewed in plan view. Each of the electronic slots is configured to physically and operably receive an electronic card. Each of the electronic slots is electrically connected to the input/output device for electrical communication between the electronic card and the input/output device.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: March 15, 2016
    Assignee: Artesyn Embedded Computing, Inc.
    Inventors: Suzanne Marye Wong, Ross L. Armstrong, Martin Peter John Cornes, Douglas L. Sandy
  • Patent number: 8316341
    Abstract: A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from predetermined design options for custom circuit boards. The hardware description language (HDL) module generates HDL corresponding to the design specifications and outputs the HDL to a circuit board producer.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: November 20, 2012
    Assignee: Emerson Network Power—Embedded Computing, Inc.
    Inventors: Douglas L. Sandy, Shlomo Pri-Tal
  • Publication number: 20110066992
    Abstract: A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from predetermined design options for custom circuit boards. The hardware description language (HDL) module generates HDL corresponding to the design specifications and outputs the HDL to a circuit board producer.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Applicant: EMERSON NETWORK POWER - EMBEDDED COMPUTING, INC.
    Inventors: Douglas L. Sandy, Shlomo Pri-Tal
  • Patent number: 7620047
    Abstract: A method of transporting a RapidIO packet (135) from an initiator RapidIO domain (102) over an IP packet network (110) to a receiver RapidIO domain (104) can include the initiator RapidIO domain creating the RapidIO packet and reading a destination domain ID (483) of the RapidIO packet, where the destination domain ID corresponds to the receiver RapidIO domain. The destination domain ID is mapped to a receiver RapidIO domain IP address (473). The RapidIO packet is encapsulated in an IP packet (436) and the IP packet is communicated to the receiver RapidIO domain over the IP packet network.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: November 17, 2009
    Assignee: Emerson Network Power - Embedded Computing, Inc.
    Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
  • Patent number: 7532616
    Abstract: A multi-service platform system, includes a backplane (104), a switched fabric (106) on the backplane, and at least one of a VMEbus network and a PCI network coincident with the switched fabric on the backplane. A payload module (102) has one of a 3U form factor, a 6U form factor and a 9U form factor, where the payload module is communicatively coupled with the backplane using the switched fabric and at least one of the VMEbus network and the PCI network. At least one multi-gigabit connector (118) is coupled to a rear edge (119) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface the payload module to the backplane, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload module through the at least one multi-gigabit connector. A storage module (112, 113) is coupled to the payload module, where the storage module is coupled to communicate with the switched fabric.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: May 12, 2009
    Assignee: Emerson Network Power - Embedded Computing, Inc.
    Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
  • Patent number: 7516263
    Abstract: A configurable switching device includes a switch card coupled to interface with a backplane of a computer chassis, a plurality of PCI-Express switching elements coupled to the switch card, and a configuration means coupled to the switch card, where the configuration means is operable to configure and reconfigure the plurality of PCI-Express switching elements to operate in a plurality of directional fabric domains, and where each of the plurality of PCI-Express switching elements can operate in only one of the plurality of directional fabric domains at a time.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: April 7, 2009
    Assignee: Emerson Network Power - Embedded Computing, Inc.
    Inventors: Douglas L. Sandy, Scott J. Fabini
  • Publication number: 20080313605
    Abstract: A method (400) of generating computer program code (108). The method can include receiving an indicator that identifies a desired amount of memory to be used for executing the computer program code. At least one identifier for at least a first algorithm (114,116,118) to be implemented by the computer program code can be received, and a version of the first algorithm that is optimized for the desired amount of memory to be used can be identified. Syntax for the identified version of the algorithm can be combined with syntax of a code template (122).
    Type: Application
    Filed: June 14, 2007
    Publication date: December 18, 2008
    Applicant: MOTOROLA, INC.
    Inventor: Douglas L. Sandy
  • Patent number: 7443844
    Abstract: A switched fabric mezzanine storage module (560) includes a storage module (562) and a switched fabric connector (563) coupled to the storage module. The storage module is coupled to directly communicate with a switched fabric (506), where the switched fabric storage mezzanine module is coupled to a payload module (502) having one of a 3U form factor, a 6U form factor and a 9U form factor. The payload module can include at least one multi-gigabit connector (518) coupled to a rear edge (519) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface with a backplane (504).
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: October 28, 2008
    Assignee: Emerson Network Power - Embedded Computing, Inc.
    Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
  • Patent number: 7440450
    Abstract: A multi-service platform system, includes a backplane (104), a switched fabric (106) on the backplane, and at least one of a VMEbus network and a PCI network coincident with the switched fabric on the backplane. A payload module (102) has one of a 3U form factor, a 6U form factor and a 9U form factor, where the payload module is communicatively coupled with the backplane using the switched fabric and at least one of the VMEbus network and the PCI network. At least one multi-gigabit connector (118) is coupled to a rear edge (119) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface the payload module to the backplane, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload module through the at least one multi-gigabit connector.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: October 21, 2008
    Assignee: Emerson Network Power-Embedded Computing, Inc.
    Inventors: Jeffrey M. Harris, Douglas L. Sandy, Robert C. Tufford
  • Publication number: 20080091888
    Abstract: A memory system includes a memory controller disposed on a baseboard, and a plurality of memory devices disposed on at least one memory module, where the at least one memory module is coupled to but separate from the baseboard. A memory buffer unit disposed on the baseboard, where the memory buffer unit is coupled to the memory controller, where the memory buffer unit is coupled to the at least one memory module, where the memory buffer unit is adapted to serialize and deserialize data communicated between the memory controller and the plurality of memory devices, and where the memory buffer is adapted to route the data among the plurality of memory devices.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 17, 2008
    Applicant: MOTOROLA, INC.
    Inventor: Douglas L. Sandy
  • Patent number: 7307987
    Abstract: A payload module (202) includes a payload subunit (212) coupled to the payload module, where the payload module has one of a 3U form factor, a 6U form factor and a 9U form factor. At least one multi-gigabit connector (218) is coupled to a rear edge (219) of the payload module and to the payload subunit, where the at least one multi-gigabit connector is coupled to communicatively interface the payload subunit to a backplane (204), where the backplane includes a switched fabric (206) coincident with at least one of a VMEbus network and a PCI network, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload subunit through the at least one multi-gigabit connector.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 11, 2007
    Assignee: Motorola, Inc.
    Inventors: Robert C. Tufford, Jeffrey M. Harris, Douglas L. Sandy
  • Patent number: 7295519
    Abstract: In a distributed switch fabric network (300) having a first node (302) having a first node transceiver port (305) and a second node (304) having a second node transceiver port (340), link level flow control (370) operating between the first node transceiver port and the second node transceiver port to in response to a congestion condition (321) in the second node transceiver port, wherein the link level flow control suspends transmission of one of a plurality of priority levels of packets (312) on a channel from the first node transceiver port to the second node transceiver port. The one of the plurality of priority levels of packets accumulates in one of a plurality of a transmit buffers (362) of the first transceiver port, where the one of the plurality of transmit buffers corresponds to the one of the plurality of priority levels of packets.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: November 13, 2007
    Assignee: Motorola, Inc.
    Inventors: Douglas L. Sandy, Charles C. Hill
  • Patent number: 7254039
    Abstract: A multi-service platform system (100, 200, 300, 400) includes a computer chassis (101, 201, 301, 401) having a plurality of 3U slots (205), a backplane (104) integrated in the computer chassis, a switched fabric (106) on the backplane. At least one of a VMEbus network and a PCI network are coincident with the switched fabric on the backplane. A payload module (102) having a 3U form factor is coupled to interface with one of the plurality of 3U slots, where the payload module is communicatively coupled with the backplane using the switched fabric and at least one of the VMEbus network and the PCI network. At least one multi-gigabit connector (118) is coupled to a rear edge (119) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface the payload module to the backplane, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload module through the at least one multi-gigabit connector.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: August 7, 2007
    Assignee: Motorola, Inc.
    Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
  • Patent number: 7242578
    Abstract: A bladed architecture, backplane-based network (100) having N payload slots (108) includes an N/2 slot switch module (102), wherein the N/2 slot switch module is reconfigurable to one of a left-hand slot switch configuration (603) and a right-hand slot switch configuration (605), and wherein the N/2 slot switch module is coupled to N/2 of the N payload slots such that the bladed architecture, backplane-based network is in a sub-optimal configuration (601).
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: July 10, 2007
    Assignee: Motorola, Inc.
    Inventors: Douglas L. Sandy, Mark S. Lanus, Robert C. Tufford
  • Patent number: 7154747
    Abstract: A switch module includes a board (114) having one of a 3U form factor and a 9U form factor, and a central switching resource (116) coupled to the board, where the central switching resource is coupled to operate a switched fabric (106) on a backplane (104), where the switched fabric operates coincident with at least one of a VMEbus network and a PCI network on the backplane.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 26, 2006
    Assignee: Motorola, Inc.
    Inventors: Robert C. Tufford, Jeffrey M. Harris, Douglas L. Sandy
  • Patent number: 7152126
    Abstract: A stacked 3U payload module unit (207) includes a base module (220), where the base module has a 3U form factor (229), and where the base module is coupled to directly communicate with a switched fabric (106) on a backplane (104) of a computer chassis (112), where the backplane comprises the switched fabric and a VMEbus network (108) operating concurrently. Stacked 3U payload module unit (207) can also include a stacking module (222) coupled to the base module, wherein the stacking module has the 3U form factor, wherein the stacking module is communicatively coupled to the base module through a stacking switched fabric connector (209), and wherein the stacking module is communicatively coupled to the switched fabric via the base module and the stacking switched fabric connector.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: December 19, 2006
    Assignee: Motorola, Inc.
    Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
  • Patent number: 7120725
    Abstract: A method of communicating a VMEbus transfer (235) from an initiator VMEbus domain (202) over an IP packet network (210) to a responder VMEbus domain (204) can include the initiator VMEbus domain creating the VMEbus transfer and reading a VMEbus destination address (452) of the VMEbus transfer. The VMEbus destination address can be mapped to a responder VMEbus domain IP address and the VMEbus transfer encapsulated in an IP packet (236). The IP packet can be communicated to the responder VMEbus domain over the IP packet network.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: October 10, 2006
    Assignee: Motorola, Inc.
    Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
  • Patent number: 6947391
    Abstract: An optimized network (300), includes providing a switch card topology (350) having a plurality of switching elements (305), where the plurality of switching elements are arranged to form a switch configuration (303). N number of payload interfaces (307) are coupled to the switch configuration, where each of the N number of payload interfaces is coupled to interface with one of a plurality of payload slots (308). A set of N payload module configurations (402, 502) is characterized by a sequential addition (320) of a payload module (304) into each of the plurality of payload slots, where the sequential addition of the payload module couples the payload module to the network. N number of payload interfaces are coupled to the switch configuration such that a latency function (616) is minimized for the switch configuration and the set of N payload module configurations.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: September 20, 2005
    Assignee: Motorola, Inc.
    Inventors: Douglas L. Sandy, Nitin B. Sharma