Abstract: A switch module includes a board (114) having one of a 3U form factor and a 9U form factor, and a central switching resource (116) coupled to the board, where the central switching resource is coupled to operate a switched fabric (106) on a backplane (104), where the switched fabric operates coincident with at least one of a VMEbus network and a PCI network on the backplane.

Abstract: A stacked 3U payload module unit (207) includes a base module (220), where the base module has a 3U form factor (229), and where the base module is coupled to directly communicate with a switched fabric (106) on a backplane (104) of a computer chassis (112), where the backplane comprises the switched fabric and a VMEbus network (108) operating concurrently. Stacked 3U payload module unit (207) can also include a stacking module (222) coupled to the base module, wherein the stacking module has the 3U form factor, wherein the stacking module is communicatively coupled to the base module through a stacking switched fabric connector (209), and wherein the stacking module is communicatively coupled to the switched fabric via the base module and the stacking switched fabric connector.

Abstract: A method of communicating a VMEbus transfer (235) from an initiator VMEbus domain (202) over an IP packet network (210) to a responder VMEbus domain (204) can include the initiator VMEbus domain creating the VMEbus transfer and reading a VMEbus destination address (452) of the VMEbus transfer. The VMEbus destination address can be mapped to a responder VMEbus domain IP address and the VMEbus transfer encapsulated in an IP packet (236). The IP packet can be communicated to the responder VMEbus domain over the IP packet network.

Abstract: An optimized network (300), includes providing a switch card topology (350) having a plurality of switching elements (305), where the plurality of switching elements are arranged to form a switch configuration (303). N number of payload interfaces (307) are coupled to the switch configuration, where each of the N number of payload interfaces is coupled to interface with one of a plurality of payload slots (308). A set of N payload module configurations (402, 502) is characterized by a sequential addition (320) of a payload module (304) into each of the plurality of payload slots, where the sequential addition of the payload module couples the payload module to the network. N number of payload interfaces are coupled to the switch configuration such that a latency function (616) is minimized for the switch configuration and the set of N payload module configurations.

Abstract: An optimized network (300), includes providing a switch card topology (350) having a plurality of switching elements (305), where the plurality of switching elements are arranged to form a switch configuration (303). N number of payload interfaces (307) are coupled to the switch configuration, where each of the N number of payload interfaces is coupled to interface with one of a plurality of payload slots (308). A set of N payload module configurations (402, 502) is characterized by a sequential addition (320) of a payload module (304) into each of the plurality of payload slots, where the sequential addition of the payload module couples the payload module to the network. N number of payload interfaces are coupled to the switch configuration such that a latency function (616) is minimized for the switch configuration and the set of N payload module configurations.

Abstract: In a distributed switch fabric network (300) having a first node (302) having a first node transceiver port (305) and a second node (304) having a second node transceiver port (340), link level flow control (370) operating between the first node transceiver port and the second node transceiver port to in response to a congestion condition (321) in the second node transceiver port, wherein the link level flow control suspends transmission of one of a plurality of priority levels of packets (312) on a channel from the first node transceiver port to the second node transceiver port. The one of the plurality of priority levels of packets accumulates in one of a plurality of a transmit buffers (362) of the first transceiver port, where the one of the plurality of transmit buffers corresponds to the one of the plurality of priority levels of packets.

Abstract: A bladed architecture, backplane-based network (100) having N payload slots (108) includes an N/2 slot switch module (102), wherein the N/2 slot switch module is reconfigurable to one of a left-hand slot switch configuration (603) and a right-hand slot switch configuration (605), and wherein the N/2 slot switch module is coupled to N/2 of the N payload slots such that the bladed architecture, backplane-based network is in a sub-optimal configuration (601).

Abstract: A bladed architecture, backplane-based network (100) having N payload slots (108) includes an N/2 slot switch module (102), wherein the N/2 slot switch module is reconfigurable to one of a left-hand slot switch configuration (603) and a right-hand slot switch configuration (605), and wherein the N/2 slot switch module is coupled to N/2 of the N payload slots such that the bladed architecture, backplane-based network is in a sub-optimal configuration (601).

Abstract: A bladed architecture, backplane-based network (100) having N payload slots (108) includes an N/2 slot switch module (102), wherein the N/2 slot switch module is reconfigurable to one of a left-hand slot switch configuration (603) and a right-hand slot switch configuration (605), and wherein the N/2 slot switch module is coupled to N/2 of the N payload slots such that the bladed architecture, backplane-based network is in a sub-optimal configuration (601).

Abstract: A distributed switch fabric network (200) includes a plurality of nodes (202-210), where each of the plurality of nodes includes at least a portion of a switching function (220-228). A plurality of receiver channels (434, 436, 438) within each of the plurality of nodes, where the plurality of receiver channels are coupled to receive a plurality of packets (414, 416, 418), and where the plurality of receiver channels aggregate in a plurality of stages (451) within the node. A shared memory resource (409) within each of the plurality of nodes, wherein the shared memory resource is coupled to receive the plurality of packets from the plurality of receiver channels.