Abstract: There is provided a fan assembly comprising a motor-driven impeller arranged to generate an airflow, an air outlet arranged to emit the airflow, a plurality of sensors arranged to measure a value for each of a plurality of air quality characteristics, a display and a processor. The processor is configured to receive measured values for each of the plurality of air quality characteristics, identify one of a corresponding set of intervals within which the measured value falls and select an air quality index value associated with the identified interval. The processor is then configured to identify the highest of the selected air quality index values as a current overall air quality index value and to cause the display to display a time series plot of the current air quality index value and a number of preceding air quality index values.

Abstract: An ophthalmic imaging apparatus comprising: an illumination light source and an optical assembly for directing light from the light source into an eye of a subject; a photosensor array comprising a plurality of photosensors positioned for acquiring images of portions of a fundus of the eye; an objective lens positioned along an imaging axis intersecting a point on the fundus of the eye wherein the objective lens is positioned for refracting light that has been reflected by the fundus to form an image of the fundus on an image plane of the objective lens such that the image plane is positioned away from the photosensor array; and a microlens array comprising a plurality of microlenses wherein the microlens array is spaced away from and positioned behind the image plane and wherein the microlens array is positioned in between the image plane and the photosensor array such that each microlens in the array projects a different view of the image formed at the image plane thereby forming an array of elemental image

Abstract: There is presented a method of driving a quantum computer to find one or more states of interest of a network. In one example, the network comprising a plurality of players. The method determines a set of adjacent graphs by determining, for each graph, whether each of the other graphs are adjacent. The method defines a cost function associated with a Hamiltonian operator of the quantum computer; the cost function comprising a set of parameters determined by analysing the utilities of vertices in the set of adjacent graphs. The method further comprises outputting a plurality of control signals for driving the quantum computer wherein the control signals are associated with the set of parameters and comprise: one or more control signals for controlling the states of qubits in the quantum computer; and, one or more control signals for controlling the entanglement of qubits in the quantum computer.

Abstract: Disclosed are systems and computer implemented methods for providing quantum computing as a service. According to one embodiment the system includes a frontend computing system storing a frontend computer program, a backend computing system, and a quantum computer, the frontend computer program being a spreadsheet application configured to receive a service request from a user, the service request comprising service request parameters and input data. The frontend computing system sends the service request to the backend computing system, which is configured to encode it to a service job in a format suitable for the quantum computer to execute, and to submit the service job to the quantum computer. The quantum computer is configured to execute the service job and to provide service job results to the backend computing system, which translates them into results data and sends them to the frontend computing system.

Abstract: An ophthalmic imaging apparatus comprising: an illumination light source and an optical assembly for directing light from the light source into an eye of a subject; a photosensor array comprising a plurality of photosensors positioned for acquiring images of portions of a fundus of the eye; an objective lens positioned along an imaging axis intersecting a point on the fundus of the eye wherein the objective lens is positioned for refracting light that has been reflected by the fundus to form an image of the fund us on an image plane of the objective lens such that the image plane is positioned away from the photosensor array; and a microlens array comprising a plurality of microlenses wherein the microlens array is spaced away from and positioned behind the image plane and wherein the microlens array is positioned in between the image plane and the photosensor array such that each microlens in the array projects a different view of the image formed at the image plane thereby forming an array of elemental imag

Abstract: An ophthalmic imaging apparatus comprising: an illumination light source and an optical assembly for directing light from the light source into an eye of a subject; a photosensor array comprising a plurality of photosensors positioned for acquiring images of portions of a fundus of the eye; an objective lens positioned along an imaging axis intersecting a point on the fundus of the eye wherein the objective lens is positioned for refracting light that has been reflected by the fundus to form an image of the fund us on an image plane of the objective lens such that the image plane is positioned away from the photosensor array; and a microlens array comprising a plurality of microlenses wherein the microlens array is spaced away from and positioned behind the image plane and wherein the microlens array is positioned in between the image plane and the photosensor array such that each microlens in the array projects a different view of the image formed at the image plane thereby forming an array of elemental imag

Abstract: A method of calibration for a plenoptic camera system to determine the true size of an object feature in a light-field image of the object wherein the camera system comprises: an objective lens positioned along an imaging axis intersecting a point in the object; a photosensor positioned for acquiring images of portions of the object and a microlens array positioned in between the objective lens and the photosensor such that each microlens in the array projects a different view of the image formed at the image plane thereby forming an array of elemental images on the photosensor, the method comprising: acquiring an initial image of the object; extracting matching features from any plurality of views derived from a plurality of elemental images forming the initial image; and calculating at least one functional relationship between two or more views having matching features.

Abstract: An automatic fluid mixing and dispensing apparatus using a minimum of two powered actuating mechanisms to retrieve fluids from a plurality of fluid containers, mix said fluids, and dispense said fluids into a plurality of dispensed fluid containers. Fluids are stored until requested and mixed in accordance with operator input.

Abstract: An ophthalmic imaging apparatus comprising: an illumination light source and an optical assembly for directing light from the light source into an eye of a subject; a photosensor array comprising a plurality of photosensors positioned for acquiring images of portions of a fundus of the eye; an objective lens positioned along an imaging axis intersecting a point on the fundus of the eye wherein the objective lens is positioned for refracting light that has been reflected by the fundus to form an image of the fund us on an image plane of the objective lens such that the image plane is positioned away from the photosensor array; and a microlens array comprising a plurality of microlenses wherein the microlens array is spaced away from and positioned behind the image plane and wherein the microlens array is positioned in between the image plane and the photosensor array such that each microlens in the array projects a different view of the image formed at the image plane thereby forming an array of elemental imag

Abstract: A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Abstract: Systems and methods to route packets of information within an integrated circuit, across one or more boards, racks, blades, and/or chassis, and/or across a connected network of packet processing engines include various modes of operation. Packets are routed to their destination, for example an individual packet processing engine. The packets of information include address-mode indicators, one or more destination port indicators, and/or (long-distance) addresses.

Abstract: An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. Locally, within an individual memory, the virtual space may be composed of discontinuous “real” segments or “chunks” within the memory, allowing bad blocks of memory to be bypassed without alteration of the virtual addresses. The delays and additional bus traffic associated with translating from virtual to real addresses are substantially reduced or eliminated.

Abstract: A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Abstract: A data collecting instrument including an input coupled with an output network port of a processing device, the input configured to receive a destination address of each data packet transmitted from the output network port, where the processing device is connected to a plurality of processing devices and is configured to transmit data packets from output network ports of the processing device to other devices of the plurality; one or more address registers configured to store information about a destination address range; a counter register configured to store a counter value; and digital circuitry coupled with the input, the one or more address registers, and the counter register; the digital circuitry configured to (i) determine, based on the information stored in the one or more address registers, that the destination address is within the destination address range; and (ii) increment the counter value stored in the counter register.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: A multiprocessor architecture utilizing direct memory access (DMA) processors that execute programmed code to feed data to one or more processor cores in advance of those cores requesting data. Stalls of the processor cores are minimized by continually feeding new data directly into the data registers within the cores. When different data is needed, the processor cores can redirect a DMA processor to execute a different feeder program, or to jump to a different point in the feeder program it is already executing. The DMA processors can also feed executable instructions into the instruction pipelines of the processor cores, allowing the feeder program to orchestrate overall processor operations.

Abstract: A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Abstract: A computing system includes a plurality of computing resources that communicate with each other using network on a chip architecture. One of the plurality of computing resources is attached to memory external to the computing system through an external memory interface. The memory-attached computing resource is configured to read data from the memory and modify the read data prior to either writing the modified data back to the memory, or transmitting the modified data to one or more other of the computing resources, or both.

Abstract: In a computing system where an incoming packet can be written directly into one or more local registers of a processing unit, a packet interface routes packets arriving at a computing system to the local registers of the processing unit or to a memory shared by multiple processing units. The shared memory includes a portion configured as a first-in, first-out (FIFO) buffer for storing packets arriving for the processing unit when its local registers are full. The stored packets are then delivered to the processing unit's one or more registers when the registers become available.