Abstract: Systems and methods may be provided to support memory access by packet communication and/or direct memory access. In one aspect, a memory controller may be provided for a processing device containing a plurality of computing resources. The memory controller may comprise a first interface to be coupled to a router. The first interface may be configured to transmit and receive packets. Each packet may comprise a header that may contain a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol. The memory controller may further comprise a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory and a controller core coupled to the first interface. The controller core may be configured to decode a packet received at the first interface and perform an operation specified in the received packet.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for implementing an intelligence aggregation system. One of the methods includes receiving, by an agent, one or more goal criteria. A search to identify one or more other agents in the system is performed. Connections with the one or more other agents are established, with each connection having an initial weight. Data outputs generated by each connected agent are received to iteratively update a model using the received data outputs and associated weights. If the current model generated from current weights for the connections of the one or more connected agents satisfies the one or more goal criteria, the output of the current model is published to a search engine.

Abstract: A computing system includes a plurality of computing resources that communicate with each other using network on a chip architecture. One of the plurality of computing resources is attached to memory external to the computing system through an external memory interface. The memory-attached computing resource is configured to read data from the memory and modify the read data prior to either writing the modified data back to the memory, or transmitting the modified data to one or more other of the computing resources, or both.

Abstract: In a computing system where an incoming packet can be written directly into one or more local registers of a processing unit, a packet interface routes packets arriving at a computing system to the local registers of the processing unit or to a memory shared by multiple processing units. The shared memory includes a portion configured as a first-in, first-out (FIFO) buffer for storing packets arriving for the processing unit when its local registers are full. The stored packets are then delivered to the processing unit's one or more registers when the registers become available.

Abstract: An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. Locally, within an individual memory, the virtual space may be composed of discontinuous “real” segments or “chunks” within the memory, allowing bad blocks of memory to be bypassed without alteration of the virtual addresses. The delays and additional bus traffic associated with translating from virtual to real addresses are substantially reduced or eliminated.

Abstract: Combinational circuits in a microprocessor execute instructions to perform permutations on bits of a source byte in a single clock cycle. Each bit in the source byte is permuted in accordance with a permutation map. The only storage within the processor core required to execute these instructions is that needed to hold the source byte, the permutation map, and the result byte. Using the permutation instructions and byte swap instructions, a wide variety of permutation operations can be performed on a word, which in the example circuits is 32 bits.

Abstract: A multiprocessor architecture utilizing direct memory access (DMA) processors that execute programmed code to feed data to one or more processor cores in advance of those cores requesting data. Stalls of the processor cores are minimized by continually feeding new data directly into the data registers within the cores. When different data is needed, the processor cores can redirect a DMA processor to execute a different feeder program, or to jump to a different point in the feeder program it is already executing. The DMA processors can also feed executable instructions into the instruction pipelines of the processor cores, allowing the feeder program to orchestrate overall processor operations.

Abstract: A data collecting instrument including an input coupled with an output network port of a processing device, the input configured to receive a destination address of each data packet transmitted from the output network port, where the processing device is connected to a plurality of processing devices and is configured to transmit data packets from output network ports of the processing device to other devices of the plurality; one or more address registers configured to store information about a destination address range; a counter register configured to store a counter value; and digital circuitry coupled with the input, the one or more address registers, and the counter register; the digital circuitry configured to (i) determine, based on the information stored in the one or more address registers, that the destination address is within the destination address range; and (ii) increment the counter value stored in the counter register.

Abstract: A network on a chip processor uses uniform addressing for both conventional memory and operand registers. The processor contains a large number of processing elements (e.g., 256). Each processing element has a number (e.g., 200) of operand registers to which it has direct, high-speed (e.g., single clock-cycle) access. Each of these operand registers is also assigned a global memory address, so other processing elements can read or write those operand registers as if they were located in main memory. Software that expects communication between processing elements to happen via memory can use memory-based reads/writes, but gain substantial speed by writing that data directly to the operand registers used for execution of instructions by the target processor.

Abstract: A computer network may comprise a plurality of computing devices. In one example, a method may be provided for discovering topology of the computer network. The method may comprise sending, by a host computing device of the computing network, a neighbor discovery packet to each network interface of the host that has a connection, receiving a reply packet responding to the neighbor discovery packet, building a neighbor map for all neighbor computing devices to the host, sending a connection discovery packet to each network interface of the host that has a connection, receiving reply packets responding to the connection discovery packet, and building a connection map for connections among computing devices based on the information in the reply packets.

Abstract: Systems and methods to process packets of information use an on-chip information processing system configured to receive, resolve, convert, and/or transmit packets of different packet-types in accordance with different protocols. A first packet-type may use a protocol for wired local-area-networking (LAN) technologies, such as Ethernet. A second packet-type may use a proprietary protocol. The proprietary protocol may be used to exchange information with one or more packet processing engines, such as neural processing engines.

Abstract: Systems and methods may be provided to support memory access by packet communication and/or direct memory access. In one aspect, a memory controller may be provided for a processing device containing a plurality of computing resources. The memory controller may comprise a first interface to be coupled to a router. The first interface may be configured to transmit and receive packets. Each packet may comprise a header that may contain a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol. The memory controller may further comprise a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory and a controller core coupled to the first interface. The controller core may be configured to decode a packet received at the first interface and perform an operation specified in the received packet.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: Systems and methods may be provided to support memory access by packet communication and/or direct memory access. In one aspect, a memory controller may be provided for a processing device containing a plurality of computing resources. The memory controller may comprise a first interface to be coupled to a router. The first interface may be configured to transmit and receive packets. Each packet may comprise a header that may contain a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol. The memory controller may further comprise a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory and a controller core coupled to the first interface. The controller core may be configured to decode a packet received at the first interface and perform an operation specified in the received packet.

Abstract: Systems and methods to route packets of information within an integrated circuit, across one or more boards, racks, blades, and/or chassis, and/or across a connected network of packet processing engines include various modes of operation. Packets are routed to their destination, for example an individual packet processing engine. The packets of information include address-mode indicators, one or more destination port indicators, and/or (long-distance) addresses.

Abstract: A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Abstract: Systems and methods may be provided to support memory access by packet communication and/or direct memory access. In one aspect, a memory controller may be provided for a processing device containing a plurality of computing resources. The memory controller may comprise a first interface to be coupled to a router. The first interface may be configured to transmit and receive packets. Each packet may comprise a header that may contain a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol. The memory controller may further comprise a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory and a controller core coupled to the first interface. The controller core may be configured to decode a packet received at the first interface and perform an operation specified in the received packet.

Abstract: A computer network may comprise a plurality of computing devices. In one example, a method may be provided for discovering topology of the computer network. The method may comprise sending, by a host computing device of the computing network, a neighbor discovery packet to each network interface of the host that has a connection, receiving a reply packet responding to the neighbor discovery packet, building a neighbor map for all neighbor computing devices to the host, sending a connection discovery packet to each network interface of the host that has a connection, receiving reply packets responding to the connection discovery packet, and building a connection map for connections among computing devices based on the information in the reply packets.

Abstract: Systems and methods for synchronization within a processing system use events and/or signals to indicate whether certain buffers (or other system components) are idle. New tasks may be assigned to individual processing elements once they are deemed idle by virtue of certain buffers or components being idle.

Abstract: Systems and methods may be provided to execute a plurality of computation tasks across a plurality of computing resources of a computing system. In one aspect, a computer-implemented method may execute a software application comprising a plurality of tasks on a computing system. The method may comprise loading the software application into the computing system, assigning the plurality of tasks to a plurality of computing resources of the computing system according to a first assignment, executing the plurality of tasks on the plurality of computing resources according to the first assignment. Each processing resource may be configured to generate and collect system activity monitoring (SAM) data. The method may further comprise collecting the SAM data from the plurality of processing resources, performing an analysis of the first assignment based on the collected SAM data and determining an adjustment to the first assignment based on the analysis.