Patents by Inventor Douglas R. Moran
Douglas R. Moran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9766683Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.Type: GrantFiled: September 20, 2016Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, Sm M. Rahman, Jawad Haj-Yihia, Alon Naveh, Ohad Falik
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Publication number: 20170010648Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.Type: ApplicationFiled: September 20, 2016Publication date: January 12, 2017Inventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, Sm M. Rahman, Jawad Haj-Yihia, Alon Naveh, Ohad Falik
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Patent number: 9477627Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.Type: GrantFiled: December 26, 2012Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, SM M. Rahman, Jawad Haj-Yihia, Alon Naveh, Ohad Falik
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Patent number: 9152205Abstract: A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.Type: GrantFiled: August 28, 2012Date of Patent: October 6, 2015Assignee: Intel CorporationInventors: Ohad Falik, Eliezer Weissmann, Alon Naveh, Michael Mishaeli, Nadav Shulman, Robert E. Gough, Erik C. Bjorge, Douglas R. Moran, Peter A. Dice
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Patent number: 9098561Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.Type: GrantFiled: August 30, 2011Date of Patent: August 4, 2015Assignee: Intel CorporationInventors: Dorit Shapira, Efraim Rotem, Douglas R. Moran
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Patent number: 9092632Abstract: A method, apparatus, machine-readable medium, and system are disclosed. In one embodiment the method includes a processor. The processor includes switching a platform firmware update mechanism located in a computer platform to a platform firmware armoring technology (PFAT) mode on a boot of the computer platform. The computer platform includes a platform firmware storage location that stores a platform firmware. The method then persistently locks the platform firmware storage location in response to the platform firmware update mechanism switching to the PFAT mode. When persistently locked, writes are only allowed to the platform firmware storage location by an Authenticated Code Module in the running platform and only after a platform firmware update mechanism unlocking procedure.Type: GrantFiled: March 15, 2013Date of Patent: July 28, 2015Assignee: Intel CorporationInventors: Allen R. Wishman, Sergiu D. Ghetie, Michael Neve De Mevergnies, Ulhas S. Warrier, Adil Karrar, Douglas R. Moran, Kirk Brannock
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Publication number: 20140181352Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Inventors: Shaun M. Conrad, William Knolla, Douglas R. Moran, SM M. RAHMAN, JAWAD HAJ-YIHIA, ALON NAVEH, OHAD FALIK
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Publication number: 20140068302Abstract: A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.Type: ApplicationFiled: August 28, 2012Publication date: March 6, 2014Inventors: Ohad Falik, Eliezer Weissmann, Alon Naveh, Michael Mishaeli, Nadav Shulman, Robert E. Gough, Erik C. Bjorge, Douglas R. Moran, Peter A. Dice
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Patent number: 8650427Abstract: Embodiments of methods and apparatus for entering an activity alignment on state from an activity alignment off state; masking one or more traffic flows that are received during at least a part of the activity alignment on state; and entering the activity alignment off state from the activity alignment on state, after being in the activity alignment on state for at least a first time period, based at least in part on said masking the one or more traffic flows. Additional variants and embodiments are also disclosed.Type: GrantFiled: March 31, 2011Date of Patent: February 11, 2014Assignee: Intel CorporationInventors: William Knolla, Douglas R. Moran, Neil W. Songer
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Patent number: 8522322Abstract: A method, apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the method includes is a processor. The processor includes switching a platform firmware update mechanism located in a computer platform to a platform firmware armoring technology (PFAT) mode on a boot of the computer platform. The computer platform includes a platform firmware storage location that stores a platform firmware. The method then persistently locks the platform firmware storage location in response to the platform firmware update mechanism switching to the PFAT mode. When persistently locked, writes are only allowed to the platform firmware storage location by an Authenticated Code Module in the running platform and only after a platform firmware update mechanism unlocking procedure.Type: GrantFiled: September 22, 2010Date of Patent: August 27, 2013Assignee: Intel CorporationInventors: Allen R. Wishman, Sergiu D. Ghetie, Michael Neve De Mevergnies, Ulhas S. Warrier, Adil Karrar, Douglas R. Moran, Kirk Brannock
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Publication number: 20130219191Abstract: A method, apparatus, machine-readable medium, and system are disclosed. In one embodiment the method includes a processor. The processor includes switching a platform firmware update mechanism located in a computer platform to a platform firmware armoring technology (PFAT) mode on a boot of the computer platform. The computer platform includes a platform firmware storage location that stores a platform firmware. The method then persistently locks the platform firmware storage location in response to the platform firmware update mechanism switching to the PFAT mode. When persistently locked, writes are only allowed to the platform firmware storage location by an Authenticated Code Module in the running platform and only after a platform firmware update mechanism unlocking procedure.Type: ApplicationFiled: March 15, 2013Publication date: August 22, 2013Inventors: Allen R. Wishman, Sergiu D. Ghetie, Michael Neve De Mevergnies, Ulhas S. Warrier, Adil Karrar, Douglas R. Moran, Kirk Brannock
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Publication number: 20130054179Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Inventors: Dorit Shapira, Efraim Rotem, Douglas R. Moran
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Publication number: 20120254644Abstract: Embodiments of methods and apparatus for entering an activity alignment on state from an activity alignment off state; masking one or more traffic flows that are received during at least a part of the activity alignment on state; and entering the activity alignment off state from the activity alignment on state, after being in the activity alignment on state for at least a first time period, based at least in part on said masking the one or more traffic flows. Additional variants and embodiments are also disclosed.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Inventors: William Knolla, Douglas R. Moran, Neil W. Songer
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Publication number: 20120072734Abstract: A method, apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the method includes is a processor. The processor includes switching a platform firmware update mechanism located in a computer platform to a platform firmware armoring technology (PFAT) mode on a boot of the computer platform. The computer platform includes a platform firmware storage location that stores a platform firmware. The method then persistently locks the platform firmware storage location in response to the platform firmware update mechanism switching to the PFAT mode. When persistently locked, writes are only allowed to the platform firmware storage location by an Authenticated Code Module in the running platform and only after a platform firmware update mechanism unlocking procedure.Type: ApplicationFiled: September 22, 2010Publication date: March 22, 2012Inventors: Allen R. Wishman, Sergiu D. Ghetie, Michael Neve De Mevergnies, Ulhas S. Warrier, Adil Karrar, Douglas R. Moran, Kirk Brannock
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Patent number: 7610611Abstract: A prioritized address decoder has been disclosed. One embodiment of the prioritized address decoder includes a first comparator to compare a destination device address of data with a first address range associated with a first device and a second comparator coupled to the first comparator to compare the destination device address with a second address range associated with a second device, wherein the data is sent to the second device in response to a first output of the first comparator and a second output of the second comparator.Type: GrantFiled: September 19, 2003Date of Patent: October 27, 2009Inventors: Douglas R. Moran, Satish Acharya, Zohar Bogin, Sean G. Galloway
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Patent number: 7139890Abstract: Methods and arrangements to interface memory are described. Many embodiments comprise comparing a transaction or access from a source to memory addresses associated with the source to determine whether an address associated with the transaction is accessible by the source. Some embodiments may comprise defining protected memory. Several embodiments may comprise defining protected memory by, for example, determining a configuration for memory. Such embodiments may comprise protecting a memory location or limiting access to memory addresses associated with a protected memory location. Some of these embodiments may comprise accessing registers to define protected memory and verifying accesses to a memory location according to the definition of protected memory. Further embodiments may comprise generating an association between a source of an access and a memory location and storing the association to facilitate access to the memory location by the source.Type: GrantFiled: April 30, 2002Date of Patent: November 21, 2006Assignee: Intel CorporationInventors: Douglas R. Moran, Clifford D. Hall, Thomas A. Piazza, Richard W. Jensen
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Patent number: 6738869Abstract: Arrangements for maintaining out-of-order queue cache coherency and for prevention of memory write starvation.Type: GrantFiled: August 29, 2000Date of Patent: May 18, 2004Assignee: Intel CorporationInventors: Douglas R. Moran, Thomas C. Brown, Kenneth B. Oliver
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Publication number: 20030204693Abstract: Methods and arrangements to interface memory are described. Many embodiments comprise comparing a transaction or access from a source to memory addresses associated with the source to determine whether an address associated with the transaction is accessible by the source. Some embodiments may comprise defining protected memory. Several embodiments may comprise defining protected memory by, for example, determining a configuration for memory. Such embodiments may comprise protecting a memory location or limiting access to memory addresses associated with a protected memory location. Some of these embodiments may comprise accessing registers to define protected memory and verifying accesses to a memory location according to the definition of protected memory. Further embodiments may comprise generating an association between a source of an access and a memory location and storing the association to facilitate access to the memory location by the source.Type: ApplicationFiled: April 30, 2002Publication date: October 30, 2003Inventors: Douglas R. Moran, Clifford D. Hall, Thomas A. Piazza, Richard W. Jensen
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Patent number: 6618770Abstract: A method and apparatus are provided for performing address translation in an input/output (I/O) expansion bridge. The I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit. The first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports. The first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system. The second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device. The address translation unit is coupled to the first interface unit and the second interface unit. The address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.Type: GrantFiled: May 9, 2002Date of Patent: September 9, 2003Assignee: Intel CorporationInventors: Raman Nayyar, Douglas R. Moran, Leonard W. Cross
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Patent number: 6615374Abstract: An integrated circuit device performs first and next error identification. An error condition associated with an integrated circuit device function is detected. Whether the detected error condition is a first detected error condition is determined, and, if so, the detected error condition is identified as the first detected error condition. Otherwise, the detected error condition is identified as a next detected error condition. A first detected error condition may be recorded in a first error status register, and a next detected error condition may be recorded in a next error status register.Type: GrantFiled: August 30, 1999Date of Patent: September 2, 2003Assignee: Intel CorporationInventor: Douglas R. Moran