Patents by Inventor Douglas R. Moran

Douglas R. Moran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation
    Patent number: 6457068
    Abstract: A method and apparatus are provided for performing address translation in an input/output (I/O) expansion bridge. The I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit. The first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports. The first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system. The second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device. The address translation unit is coupled to the first interface unit and the second interface unit. The address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: September 24, 2002
    Assignee: Intel Corporation
    Inventors: Raman Nayyar, Douglas R. Moran, Leonard W. Cross
  • Input/output (I/O) address translation in a bridge proximate to a local I/O bus
    Publication number: 20020129187
    Abstract: A method and apparatus are provided for performing address translation in an input/output (I/O) expansion bridge. The I/O expansion bridge includes a first interface unit, a second interface unit, and an address translation unit. The first interface unit is configured to be coupled to a system memory and I/O controller through one or more I/O ports. The first interface unit enables data transfers over the one or more I/O ports to or from the main memory of a computer system. The second interface unit provides bus control signals and addresses to enable data transfers over a bus to or from a peripheral device. The address translation unit is coupled to the first interface unit and the second interface unit. The address translation unit translates addresses associated with transactions received on the second interface by accessing a local memory containing physical addresses of pages in the main memory of the computer system.
    Type: Application
    Filed: May 9, 2002
    Publication date: September 12, 2002
    Inventors: Raman Nayyar, Douglas R. Moran, Leonard W. Cross
  • Memory system and unique memory chip allowing island interlace
    Patent number: 5278800
    Abstract: A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: January 11, 1994
    Assignee: International Business Machines Corporation
    Inventors: Warren W. Grunbok, Billy J. Knowles, William R. Milani, Douglas R. Moran, Dale E. Pontius, Donald W. Price, Robert Tamlyn, Yee-Ming Ting, De Tran, Henry Yeh