Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: A digital-to-analog converter having a semiconductor resistor strip with plural voltage taps. One voltage tap formed of the semiconductor material defines a nonzero reference voltage for the converter. An auto-zeroing amplifier is utilized to charge a coupling capacitor to the nonzero reference voltage. In the conversion process, the analog voltages at the other voltage taps of the resistor strip are selected via a switch arrangement and coupled to the coupling capacitor. The linearity of the digital-to-analog converter is thus more independent of parasitic resistances that may be formed in the ground connection to the resistor string.

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals.

Abstract: An auto-calibrating companion bit successive approximation system uses sampling and balancing capacitors in a charge redistribution digital-to-analog converter having multi-valued capacitors of magnitudes enabling redundant expression of electric charge values. Companion bits are used with sets of balancing capacitors for successive approximation of sampling voltages. A charge redistribution digital-to-analog converter has a sampling and balancing capacitors including associated companion bit capacitors represented by digital weights which are saved in memory. A non-binary weighted set of capacitors provides redundancy in a charge redistribution digital-to-analog converter employed in a successive approximation register architecture.

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: An analog-to-digital converter configurable for converting both differential and single-ended analog signals. Charge sharing between two input capacitors and a DAC capacitor allow the full dynamic range of the ADC device to be used when full scale differential analog input signals are converted. When configured for single-ended operation, charge sharing of the half scale single-ended input analog voltage occurs between one input capacitor and the DAC capacitor to allow the full dynamic range of the ADC device to again be utilized.

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract: An analog-to-digital converter amplifier that is configurable with one gain for driving one terminal of a sampling capacitor while the other terminal is sampled to an analog input signal during one time period, and configurable with a different gain for comparing the analog sample with a DAC-generated reference voltage during a second time period.

Abstract: A programmable gain circuit for analog-to-digital converter. A switched capacitor network capacitively couples an analog reference from a DAC to a comparator so that the sampled amplitude of the input analog signal can be compared with said analog reference. The ratio of the capacitance of the sampling capacitor to that of the switched capacitor network establishes an effective gain to the analog signal being converted.

Abstract: A multistage comparator is calibrated to remove quasi-autozero voltages derived from the native comparator offset and autozero switch charge injection offsets. A multistage comparator includes a plurality of series connected amplifiers each having a programmable source, and further including a latch. A calibration method for a multistage comparator includes calibrating the first of a series of amplifiers first for both voltage offset and charge injection errors thereby to remove the quasi-autozero voltage and charge injection offsets.

Abstract: A ratiometric converter is provided that is comprised of a dual converter system utilizing a first converter (36) and a second converter (38). The second converter (38) is operable to receive the input voltage from a load cell (10) on sense lines (12) and (14) and compare them with an internal reference. Similarly, the first A/D converter (36) is operable to receive the reference voltage to the load cell (10) and compare it with the internal reference. The output of each of the converters (36) and (38) is then input to subtraction circuits (78) and (84), respectively, in the digital domain. In a calibration mode, switches (72) and (73) shorts the reference nodes in the load cell (10) together to determine the non-ratiometric offsets., These offsets are then stored in registers (80) and (86) for the reference voltage and the input voltage, respectively.

Abstract: An optical communication system includes two optical modems (12) and (14) which are disposed at either end of an optical fiber data link (10). The optical modems (12) and (14) communicate through LEDs (16) and (18), respectively, with the fiber data link (10). Each of the optical modems (12) and (14) on start-up are peerless and do not operate in either a master or a slave configuration. A ping-pong transmission format is utilized with transmitted packets of data. When one of the optical modems (12) or (14) detects a transmitted packet from the other, it locks up to the transmitted packet with a phase lock loop and takes on slave status. This slave status is transmitted back to the fiber data link (10) in another transmitted packet. The transmitted packet from the slave device is then adjusted time relative to the machine cycle of the slave device until the packet is received by the other optical modem.

Abstract: A calibration circuit for a linear channel of an optical modem includes circuitry interconnected to the linear channel for causing the linear channel to oscillate. Circuitry is interconnected to the output of the linear channel for monitoring the bandwidth of the linear channel during oscillation and for generating output pulses. The output pulses are counted and are utilized for generating an adjustment signal applied to the linear channel for adjusting the bandwidth of the linear channel.