Abstract: A voltage limiter includes a first FET of a given polarity having the source electrode adapted to be connected to a positive supply terminal. There is a second FET of an opposite polarity to said first and having the source electrode adapted to be connected to a supply terminal which is negative with respect to said positive terminal. The voltage at each terminal may typically vary during operation. There is a voltage clamp means connected between the drain electrodes of said first and second FETs with the gate electrode of the first FET connected to the drain electrode of the second FET and with the gate electrode of the second FET connected to the drain electrode of the first FET, to cause the voltage across said voltage clamping means to remain constant in spite of variations in said positive and negative supplies. The voltage across the drain electrodes of the FETs is further employed as a biasing source for additional logic circuits.

Abstract: A circuit whose output is asymmetrical whereby the circuit makes a transition from a first state to a second state more slowly than from the second state to the first state a preset towards the second state prior to the application of data input signals to the circuit.

Abstract: A first output transistor, operated in the common emitter mode, has its conduction path connected between an output terminal and a first point of operating potential. A phase splitting transistor whose base is coupled to a signal input terminal supplies a turn-on current to the base of the first transistor for one value of input signal and interrupts the flow for another value of input signal. The discharge of residual charge on the base of the first transistor and its speedy turn-off is accomplished by means of a clamping transistor whose collector-to-emitter path is connected between the base and emitter of the first transistor and which is turned on concurrently with the turn-off of the phase splitting transistor.

Abstract: A bias network includes a transistor connected at its emitter to a first point of operating potential. A current passing means is connected between a second point of operating potential and an intermediate point. A first diode is connected between the intermediate point and the base of the transistor and a second diode is connected between the intermediate point and the collector of the transistor for producing at the collector a regulated bias voltage. Means are included to selectively turn-off the transistor for causing the equivalent impedance at its collector to become high.

Abstract: A ratioed power on reset apparatus utilizing two pairs of field effect transistors as voltage dividers to generate a power on reset signal which tracks the waveshape of an applied power signal with a slot rise time.