Abstract: A method for plasma treating an etched opening formed in a porous low-K material to improve barrier layer integrity including providing a substrate comprising an etched opening formed in an insulating dielectric layer including porous low-K silicon oxide according to an overlying patterned resist layer; plasma treating according to a plasma process the etched opening to remove the resist layer and increase a surface density of the insulating dielectric layer within the etched opening; and, blanket depositing a barrier layer over the etched opening.

Abstract: A method for plasma treating an etched opening formed in a porous low-K material to improve barrier layer integrity including providing a substrate comprising an etched opening formed in an insulating dielectric layer including porous low-K silicon oxide according to an overlying patterned resist layer; plasma treating according to a plasma process the etched opening to remove the resist layer and increase a surface density of the insulating dielectric layer within the etched opening; and, blanket depositing a barrier layer over the etched opening.

Abstract: A method for fabricating a copper interconnect structure, using a low resistivity Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copper layer, an anneal procedure is used to form the Cu.sub.3 Ge intermetallic layer, with the intermetallic layer, located between the underlying titanium nitride barrier layer, and the overlying copper layer. The Cu.sub.3 Ge intermetallic layer can also be formed in situ, during deposition, if the deposition temperature exceeds 150.degree. C. Cu.sub.3 Ge layer exhibits a resistivity of about 5E-6 ohm - cm. A second iteration of this invention allows a thick copper layer to be plated on a thin copper seed layer, only on the top surface of a semiconductor substrate. This iteration, also incorporating the low resistivity, Cu.sub.3 Ge intermetallic, and the adhesive layer, prevents copper from being plated on the beveled edge of the semiconductor substrate.

Abstract: A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.

Abstract: A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.

Abstract: A method for fabricating a copper interconnect structure, using a Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following the deposition of a copper seed layer, an ion implantation procedure is performed, placing germanium ions in a copper seed layer. After deposition of a thick copper layer, an anneal cycle, performed before or after deposition of the thick copper layer, is used to create a Cu.sub.3 Ge intermetallic layer at the interface between a copper seed layer and a titanium nitride barrier layer. A second embodiment of this invention uses a tilted, germanium ion implantation procedure, used to avoid the placement of germanium ions in a copper seed layer, at the bottom of a contact hole, thus avoiding possible implantation damage, to active device regions, exposed in the bottom of the contact hole.

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a patterned first dielectric layer which defines a via accessing a contact region formed within the substrate. The patterned first dielectric layer is formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed upon the patterned first dielectric layer a blanket second dielectric layer which completely covers the patterned first dielectric layer and fills the via. The blanket second dielectric layer is formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer which is formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma.

Abstract: A defect free intermetal dielectric, IMD, and method of forming the defect free IMD are described. The IMD uses spacers formed by means of etchback of a layer of spin-on-glass, SOG. In order to use an oxide layer formed by means of plasma enhanced tetra-ethyl-ortho-silicate, PE-TEOS, as part of the IMD an oxide cap layer formed using plasma enhanced chemical vapor deposition, PE-CVD, is used to isolate the SOG spacers from the PE-TEOS formed oxide layer. By isolating the PE-TEOS formed oxide layer from the SOG spacers a reliable and defect free IMD is achieved.

Abstract: A process has been developed in which the contact area, between an overlying metal filled via structure, and an underlying metal interconnect structure, has been increased. The process features opening a via hole, in a dielectric layer, to an underlying metal interconnect structure, with the via hole being larger in width then the width of the underlying metal interconnect structure. Continued selective removal of the dielectric layer, in the via hole, results in exposure of the sides of the metal interconnect structure. Subsequent formation of an overlying metal filled via structure, in the via hole, results in an increase in contact area between the overlying metal filled via structure, and the narrow, metal interconnect structure.

Abstract: The contact hole via mask used in the manufacture of semiconductor integrated circuits is modified to produce a multiplicity of lines and spaces adjacent to the edge of an alignment mark in the via hole pattern. This line-space pattern is etched simultaneously with the contact via holes, and allows the regeneration of the alignment mark after tungsten deposition and planarization of the surface by conventional oxide etching and metallization steps.

Abstract: A self aligned contact to the substrate in the region between two gate electrodes is formed by depositing a conformal dielectric layer and patterning to form a contact window. The conductive elements of the gate electrode are not contacted because of etch rate differentials between the conformal dielectric and the insulating elements of the gate structure.

Abstract: A method is described for overcoming the non-conformity and poor step coverage incurred when materials such as metals and barrier layers are deposited into contact openings by physical-vapor-deposition(PVD) techniques such as sputtering and evaporation. Conventional PVD deposition into a vertical walled opening results in a deposit whose thickness diminishes towards the base of the opening. This causes voids when the opening is subsequently filled by chemical-vapor-deposited(CVD) tungsten as well as potential failure of the barrier material due to inadequate coverage at the base of the opening. The method utilizes a two stage reactive ion etching technique to selectively etch the upper portion of the deposited layer while protecting the lower portion with photoresist. A second deposition of barrier layer material then restores material at the top of the opening while augmenting the thickness at the base. This reduces the negative taper of the opening and allows total filling by the subsequent CVD deposition.

Abstract: A method for forming a planarized interlevel dielectric layer without degradation due to microloading effect is described. A first conformal layer of silicon dioxide is deposited overlying a conducting layer over an insulating layer on a semiconductor substrate. A second silicon dioxide layer is deposited overlying the first conformal silicon dioxide layer. A doped glass layer is deposited overlying the second silicon dioxide layer. The doped glass layer is coated with a spin-on-glass layer. The spin-on-glass layer is etched back until the interlevel dielectric layer is planarized. The microloading effects from the etching back of the spin-on-glass layer of the interlevel dielectric layer are lower than microloading effects in a conventional interlevel dielectric layer.

Abstract: This invention relates to a method for removing residual spin-on-glass (SOG) during a planarization processing step wherein the SOG is used as a sacrificial planarization medium and subjected to a full etchback to an underlying interlevel dielectric (ILD) layer. The SOG is applied over the ILD layer, and etched back into the ILD layer by reactive-ion-etching under conditions of comparable etch rates for both SOG and ILD. At endpoint there some residual pockets of SOG can be present as well as a region of SOG along the edges of the wafer where it is clamped in the etchback tool. The residual SOG must be removed completely to avoid SOG cracking after thermal processing and SOG outgassing during subsequent metal deposition. For this purpose an aqueous etch consisting of hydrofluoric acid buffered with ammonium fluoride is used.

Abstract: A process for forming narrow polycide gate structures, using a low resistance, titanium silicide layer, has been developed. The process features initially forming a high resistance, titanium silicide layer, on exposed silicon regions, formed during the high temperature, PECVD titanium procedure. After deposition of a titanium nitride layer, used to protect the underlying high resistance, titanium silicide layer from a subsequent one step RTA anneal procedure, which is next performed ?one step RTA anneal is then used! to convert the high resistance titanium silicide layer to a lower resistance titanium silicide layer. A composite insulator spacer is also used to reduce possible metal, or silicide bridging phenomena.

Abstract: A method for forming within an integrated circuit a narrow line-width high aspect ratio via through a first integrated circuit layer which resides upon a second integrated circuit layer. There is first formed upon a semiconductor substrate a second integrated circuit layer which has formed upon its surface a first integrated circuit layer. Through a first etch method, a partial via is then formed within the first integrated circuit layer to a distance of from about 2500 to about 4000 angstroms above the surface of the second integrated circuit layer. The first etch method is chosen to provide a partial via with substantially parallel sidewalls. Through a second etch method, the partial via is then etched completely through the first integrated circuit layer. The second etch method is chosen to possesses an etch selectivity ratio for the first integrated circuit layer with respect to the second integrated circuit layer of at least about 60:1.

Abstract: A defect free intermetal dielectric, IMD, and method of forming the defect free IMD are described. The IMD uses spacers formed by means of etchback of a layer of spin-on-glass, SOG. In order to use an oxide layer formed by means of plasma enhanced tetra-ethyl-ortho-silicate, PE-TEOS, as part of the IMD an oxide cap layer formed using plasma enhanced chemical vapor deposition, PE-CVD, is used to isolate the SOG spacers from the PE-TEOS formed oxide layer. By isolating the PE-TEOS formed oxide layer from the SOG spacers a reliable and defect free IMD is achieved.

Abstract: A process for forming an planar dielectric layer over metallurgy lines using an in situ multi-step electron cyclotron resonance (ECR) oxide deposition process. A substrate with metallurgy lines on its surface is covered with a protective ECR oxide layer. The novel ECR process for the protective layer does not have an argon flow and does not etch the surface (e.g., metal lines) it is deposited upon. Next, a gap-fill step is formed over the protective layer. The gap-fill step uses Argon flow and rf power to enhance the deposition in gaps and the planarization. The gap-fill layer etches the underlying protective layer but the protective layer prevents the gap-fill deposition/etch process from attacking and damaging the metallurgy lines. Next, the protective layer and the gap-fill layer sequence are repeated until the desired thickness is obtained. A thick capping protective layer and a capping gap-fill layer are used to complete the planarization process.

Abstract: A method for forming an insulator layer with enhanced uniformity when planarized through a Chemical-Mechanical Polish (CMP) planarizing process. There is first provided a semiconductor substrate having formed thereupon a patterned layer. The patterned layer has a volume density greater than the volume density of an insulator layer to be formed upon the patterned layer. The patterned layer also has a first region having a high areal density of the patterned layer and a second region having a low areal density of the patterned layer. The second region of the patterned layer is then masked. The first region of the patterned layer is then exposed to a first plasma which is capable of modifying the first region of the patterned layer such that the insulator layer will form less rapidly upon the first region of the patterned layer than upon the second region of the patterned layer. The second region of the semiconductor substrate is then unmasked and the insulator layer is formed upon the patterned layer.

Abstract: A Process for creating a planar topography and enhanced step coverage for the fabrication of contact/via holes in sub-half-micron diameter range with high height vs. dimension aspect ratio. This is accomplished by interrupting the deposition of the barrier layer in the contact/via lining with a programmed reactive ion etching process, which will protect the thin barrier lining in the bottom part of the contact hole, but will etch off and planarize the excessively thick barrier layer near the opening of the hole. The resulting barrier layers show a disrupt columnar film structure which provides better barrier during subsequent metal fill deposition process.