Abstract: A method for the fabrication of an ohmic, low resistance contact to silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for a glass insulator layer deposited on the silicon. After the glass is flowed to planarize its surface, contact holes are patterned in the glass exposing the silicon substrate. The Ti/TiN barrier metallurgy is deposited by sputtering which, because of inferior edge coverage, results in a sidewall with a negative taper. Subsequent deposition of the tungsten results in a tungsten plug with an exposed void. The method taught by this invention deposits first a thin layer of tungsten whose thickness is governed by the amount of overhang caused by the tapered sidewall. An anisotropic dry etch step is then performed to achieve a vertical sidewall of tungsten. The remaining tungsten is then deposited to fill the contact opening without the occurrence of voids.

Abstract: A Process for creating a planar topography and enhanced step coverage for the fabrication of contact/via holes in sub-half-micron diameter range with high height vs. dimension aspect ratio. This is accomplished by interrupting the deposition of the barrier layer in the contact/via lining with a programmed reactive ion etching process, which will protect the thin barrier lining in the bottom part of the contact hole, but will etch off and planarize the excessively thick barrier layer near the opening of the hole. The resulting barrier layers show a disrupt columnar film structure which provides better barrier during subsequent metal fill deposition process.