Patents by Inventor Dragan Maksimovic

Dragan Maksimovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7581120
    Abstract: A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the adaptive voltage scaling (AVS) system. The present invention provides multi-point calibration by calibrating a Reference Calibration Code (RCC) for each operating point (clock frequency) of the adaptive voltage scaling (AVS) system.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: August 25, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Mark Hartman, James T. Doyle, Dragan Maksimovic, Pasi Salmi, Juha Pennanen, Sandeep Dhar
  • Publication number: 20090066382
    Abstract: A hybrid digital pulse width modulator (DPWM) with digital delay-locked loops (DLLs) is provided. In this implementation, the digital pulse-width-modulator is synthesizable and includes a digital delay-locked loop around a delay-line to achieve constant frequency clocked operation. In this implementation, the resolution of the modulator is consistent over a wide range of process or temperature variations. The DPWM may implement trailing-edge, leading-edge, triangular, or phase-shift modulation. In an implementation suitable for DC-DC converters with synchronous rectifiers, for example, the DPWM may include two or more outputs for programmable dead-times. In another implementation, a digital pulse-width-modulator with a digital phase-locked loop is also provided.
    Type: Application
    Filed: June 13, 2008
    Publication date: March 12, 2009
    Applicant: THE REGENTS OF THE UNIVERSITY OF COLORADO
    Inventors: Vahid Yousefzadeh, Anthony Carosa, Toru Takayama, Dragan Maksimovic
  • Patent number: 7493149
    Abstract: A method for minimizing power consumption in a mobile device using cooperative adaptive voltage and threshold scaling is provided that includes receiving a supply voltage, a PMOS back bias voltage, and an NMOS back bias voltage. A clock signal is received. The clock signal is propagated through a timing comparison circuit. An output of the timing comparison circuit is examined. A determination is made regarding whether to request more power based on the output of the timing comparison circuit. A voltage control signal is sent to request more power when a determination is made to request more power based on the output of the timing comparison circuit.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: February 17, 2009
    Assignee: National Semiconductor Corporation
    Inventors: James T. Doyle, Dragan Maksimovic
  • Patent number: 7479772
    Abstract: A converter module for use as a phase in a multiphase DC-DC converter having a data bus for transferring current-sharing information is provided. The converter module includes a power stage and a controller. The power stage comprises an input for receiving an input voltage and an output for providing an output voltage and an output current. The controller is coupled to the power stage to receive a feedback signal from the power stage. The controller further comprises a data bus port configured to receive the current-sharing information from the data bus and provide updated current-sharing information to the data bus.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: January 20, 2009
    Assignee: The Regents of the University of Colorado
    Inventors: Regan A. Zane, Dragan Maksimovic, Yang Zhang
  • Publication number: 20080310200
    Abstract: An architecture is described for digital multi-phase modulators (MPM) that leads to an efficient, high performance hardware realization. The combined modulator, switching phases and output filter can be viewed as a multi-level digital to analog converter with high power output, or a power D/A, and concepts used in D/A converters are leveraged to achieve high performance and hardware efficiency. The modulator can be split into three functional blocks including a decoder that determines how many phases are on at any time, a selector that determines which phases are on at any time, and a single high resolution module that is time shared among all phases. The resulting architecture scales favorably with a large number of phases, fs, facilitates fast update rates of the input command well above the single phase switching frequency and is compatible with a wide range of known DPWM techniques for the LSB module and resolution-enhancement techniques such as dithering or ?-? modulation.
    Type: Application
    Filed: June 10, 2008
    Publication date: December 18, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF COLORADO
    Inventors: Dragan Maksimovic, Regan Zane, Anthony Carosa
  • Publication number: 20080310201
    Abstract: A digital PFC (DPFC) control approach that requires no input voltage sensing or current loop compensation is described. The approach can provide stable, low-harmonic operation over a universal input voltage range and load ranging from high-load operation in continuous conduction mode down to near-zero load. A fast voltage loop can also be incorporated into a DPFC controller to provide additional control of the power stage. A controller can be based on low-resolution DPWM and A/D converters, can be implemented without microcontroller or DSP programming, and is well suited for simple, low-cost integrated-circuit realizations.
    Type: Application
    Filed: April 30, 2008
    Publication date: December 18, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF COLORADO
    Inventor: Dragan Maksimovic
  • Patent number: 7456620
    Abstract: Systems, methods, and apparatuses are disclosed for determining dead-times in switched-mode DC-DC converters with synchronous rectifiers or other complementary switching devices. In one embodiment, for example, a controller for a DC-DC converter determines dead-times for switching devices of a synchronous rectifier or other complementary switching device of the converter in which a dead-time is derived from an output voltage or current that is already sensed and used in the output regulation of the converter. In another embodiment, a controller is provided for controlling a switched-mode DC-DC converter comprising a pair of power switches. The controller comprises an input, a reference generator, a comparator, a compensator, a dead-time sub-controller, and a modulator. In another embodiment, the controller may adjust the dead-times during the operation of the converter to adjust periodically and/or in response to changes in operating conditions.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: November 25, 2008
    Assignee: The Regents of the University of Colorado
    Inventors: Dragan Maksimovic, Vahid Yousefzadeh
  • Publication number: 20080164859
    Abstract: A digital current-mode controller for a DC-DC converter is disclosed. The controller comprises a digital current reference; and a current loop compensator adapted to receive a digital current error signal derived from a digital current sample sensed from the DC-DC converter and the digital current reference and to generate a duty-cycle command, wherein the current loop compensator comprises a low-pass filter that is used in generating the duty-cycle command. A DC-DC regulator comprising a digital current-mode controller and a method of controlling a DC-DC converter are also disclosed.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 10, 2008
    Applicant: The Regents of the University of Colorado
    Inventors: Hao Peng, Dragan Maksimovic
  • Patent number: 7315270
    Abstract: Differential delay-line analog-to-digital (A/D) converters for use in current and power sensing applications are provided. These A/D converters are well suited for a wide range of electronic applications, including over-load protection, current mode control, current sharing in digitally controlled switched-mode power supplies, power sensing, and implementation of power optimization methods in power management applications.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: January 1, 2008
    Assignee: The Regents of the University of Colorado
    Inventors: Dragan Maksimovic, Hao Peng
  • Patent number: 7271754
    Abstract: A digital pulse-width modulator is provided that receives a digital command input signal and a secondary control input signal and provides a pulse-width-modulated output signal. The pulse-width-modulated output signal comprises a pulse-width that corresponds to an integer number of slots each having a time duration. The integer number of slots corresponds to a value of the digital command signal, and the time duration is determined based upon the secondary control input signal. In one embodiment, the digital pulse-width-modulator comprises a plurality of delay cells arranged in series for propagating a clock signal through the plurality of delay cells. A time delay for each of the delay cells is determined by the secondary control input signal.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: September 18, 2007
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Dragan Maksimovic, Asif Syed, Ershad Ahmed
  • Patent number: 7196526
    Abstract: A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: March 27, 2007
    Assignee: The Regents of the University of Colorado, A Body Corporate
    Inventors: Michael Vincent, Dragan Maksimovic
  • Patent number: 7148669
    Abstract: The present invention provides a method for producing a controlled output voltage for a switching power converter under current control using pulse width modulation, the switching power converter including a predictive digital current-mode controller and a digital pulse width modulator. The current control results in an unstable output voltage, and the pulse width modulation method is selected to eliminate the instability of the output voltage.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: December 12, 2006
    Assignee: The Regents of the University of Colorado, a body corporate
    Inventors: Dragan Maksimovic, Jingquan Chen, Aleksandar Prodic, Robert W. Erickson
  • Publication number: 20060273831
    Abstract: Differential delay-line analog-to-digital (A/D) converters for use in current and power sensing applications are provided. These A/D converters are well suited for a wide range of electronic applications, including over-load protection, current mode control, current sharing in digitally controlled switched-mode power supplies, power sensing, and implementation of power optimization methods in power management applications.
    Type: Application
    Filed: March 6, 2006
    Publication date: December 7, 2006
    Inventors: Dragan Maksimovic, Hao Peng
  • Publication number: 20060239046
    Abstract: A converter module for use as a phase in a multiphase DC-DC converter having a data bus for transferring current-sharing information is provided. The converter module comprises a power stage and a controller. The power stage comprises an input for receiving an input voltage and an output for providing an output voltage and an output current. The controller is coupled to the power stage to receive a feedback signal from the power stage. The controller further comprises a data bus port configured to receive the current-sharing information from the data bus and provide updated current-sharing information to the data bus.
    Type: Application
    Filed: February 27, 2006
    Publication date: October 26, 2006
    Inventors: Regan Zane, Dragan Maksimovic, Yang Zhang
  • Publication number: 20060227861
    Abstract: A digital pulse-width modulator is provided that receives a digital command input signal and a secondary control input signal and provides a pulse-width-modulated output signal. The pulse-width-modulated output signal comprises a pulse-width that corresponds to an integer number of slots each having a time duration. The integer number of slots corresponds to a value of the digital command signal, and the time duration is determined based upon the secondary control input signal. In one embodiment, the digital pulse-width-modulator comprises a plurality of delay cells arranged in series for propagating a clock signal through the plurality of delay cells. A time delay for each of the delay cells is determined by the secondary control input signal.
    Type: Application
    Filed: February 22, 2006
    Publication date: October 12, 2006
    Inventors: Dragan Maksimovic, Asif Syed, Ershad Ahmed
  • Patent number: 7117378
    Abstract: There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a critical path in the digital processing component is determined by a level of a power supply, VDD, of the digital processing component. The adjustable power supply is capable of supplying VDD to the digital processing component. The power supply adjustment circuitry is operable to receive a first selected clock signal and adjusts the level of VDD such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first selected clock signal and a second clock edge of the first selected clock signal immediately following the first clock edge.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: October 3, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Dragan Maksimovic, Sandeep Dhar, Bruno Kranzen, Ravindra Ambatipudi
  • Patent number: 7106040
    Abstract: There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: September 12, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Dragan Maksimovic, Sandeep Dhar, Ravindra Ambatipudi, Bruno Kranzen
  • Patent number: 7079589
    Abstract: A communications system interleaves control pulses between the transitions in a serial bit stream to form an interleaved signal. The serial bit stream has a series of transitions and a series of gaps between transitions where a transition can not occur. An interleaver identifies gaps in the serial bit stream, and inserts the control pulses in the gaps to form the interleaved signal. The interleaved signal reduces the pin count when the interleaved signal is transmitted between chips.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: July 18, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Dragan Maksimovic, James Thomas Doyle
  • Publication number: 20060152204
    Abstract: Systems, methods, and apparatuses are disclosed for determining dead-times in switched-mode DC-DC converters with synchronous rectifiers or other complementary switching devices. In one embodiment, for example, a controller for a DC-DC converter determines dead-times for switching devices of a synchronous rectifier or other complementary switching device of the converter in which a dead-time is derived from an output voltage or current that is already sensed and used in the output regulation of the converter. In another embodiment, a controller is provided for controlling a switched-mode DC-DC converter comprising a pair of power switches. The controller comprises an input, a reference generator, a comparator, a compensator, a dead-time sub-controller, and a modulator. In another embodiment, the controller may adjust the dead-times during the operation of the converter to adjust periodically and/or in response to changes in operating conditions.
    Type: Application
    Filed: December 5, 2005
    Publication date: July 13, 2006
    Inventors: Dragan Maksimovic, Vahid Yousefzadeh
  • Patent number: 7061292
    Abstract: Apparatus for efficiently supplying energy to a device in a circuit, the apparatus comprising a powered device having a critical path delay; delay line operative to model said critical path delay; control logic responsive to output from said delay line and operative to generate control output; and a power converter operative to adjust supply voltage to said powered device in response to said generated control output, wherein the delay line, the control logic, and the power converter cooperate to provide first order bang-bang control of said critical path delay.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: June 13, 2006
    Assignee: The Regents of the University of Colorado
    Inventors: Dragan Maksimovic, Sandeep C. Dhar