Patents by Inventor Dragan Maksimovic

Dragan Maksimovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7024568
    Abstract: A method for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system is provided that includes providing a nominal power supply voltage to the system as a power supply voltage. A regulator clock signal is propagated through a delay line. The delay line comprises a plurality of delay cells and is operable to function based on the nominal power supply voltage. A plurality of pairs of delay cells are sampled until a first and second delay cell are identified based on the first delay cell receiving the regulator clock signal and the second delay cell failing to receive the regulator clock signal at a specified time. A reference voltage is provided to the system as the power supply voltage. The system is operated using the first and second delay cells to determine whether to adjust the power supply voltage for the system.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: April 4, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Dragan Maksimovic, Sandeep Dhar
  • Publication number: 20060055574
    Abstract: A voltage controller (150), the controller comprising: a voltage comparator (700) operative to provide a digital error signal (152); a compensator (300) operative to determine a digital control signal (154) based on said provided error signal; and a modulator (400) operative to provide a power control signal (156) based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.
    Type: Application
    Filed: December 9, 2002
    Publication date: March 16, 2006
    Inventors: Dragan Maksimovic, Benjamin Patella, Aleksandar Prodic, Sandeep Dhar
  • Publication number: 20060055414
    Abstract: A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.
    Type: Application
    Filed: August 18, 2005
    Publication date: March 16, 2006
    Applicant: University of Colorado
    Inventors: Michael Vincent, Dragan Maksimovic
  • Patent number: 6985025
    Abstract: There is disclosed control circuitry for adjusting a power supply level, VDD, of a digital processing component having varying operating frequencies. The control circuitry comprises N delay cells and power supply adjustment circuitry. The N delay cells are coupled in series, each of which has a delay D determined by a value of VDD, such that a clock edge applied to an input of a first delay cell ripples sequentially through the N delay cells. The power supply adjustment circuitry capable of adjusting VDD and is operable to (i) monitor outputs of at least a K delay cell and a K+1 delay cell, (ii) determine that the clock edge has reached an output of the K delay cell and has not reached an output of the K+1 delay cell, and (iii) generate a control signal capable of adjusting VDD in response thereto.
    Type: Grant
    Filed: January 19, 2002
    Date of Patent: January 10, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Dragan Maksimovic, Sandeep Dhar
  • Patent number: 6958721
    Abstract: A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: October 25, 2005
    Assignee: The Regents of the University of Colorado
    Inventors: Michael Vincent, Dragan Maksimovic
  • Patent number: 6944780
    Abstract: There is disclosed clock control circuitry for selectively applying a clock signal to a digital processing component wherein the clock signal is capable of being changed to a plurality of operating frequencies. The clock control circuitry is operable to (i) receive a command to change a first operating frequency to a second operating frequency, (ii) in response to the command, disable the applied clock signal, (iii) generate a test clock signal having the second operating frequency, (iv) apply the test clock signal to a power supply adjustment circuit, and (v) sense a status signal from the power supply adjustment circuit. The status signal indicates that a power supply level of the digital processing component has been adjusted to an optimum value suitable for the second operating frequency.
    Type: Grant
    Filed: January 19, 2002
    Date of Patent: September 13, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Bruno Kranzen, Dragan Maksimovic
  • Publication number: 20050168198
    Abstract: The present invention provides a method for producing a controlled output voltage for a switching power converter under current control using pulse width modulation, the switching power converter including a predictive digital current-mode controller and a digital pulse width modulator. The current control results in an unstable output voltage, and the pulse width modulation method is selected to eliminate the instability of the output voltage.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 4, 2005
    Applicant: The Regents Of The University Of Colorado, a body corporate
    Inventors: Dragan Maksimovic, Jingquan Chen, Aleksandar Prodic, Robert Erickson
  • Patent number: 6914487
    Abstract: A method for providing power management in a radio frequency power amplifier using adaptive envelope tracking is provided that includes receiving an input voltage. A power control signal is received. A feedback signal is received. An amplifier input signal is received. From the input voltage, a regulated power supply signal is generated based on the power control signal, the feedback signal, and the amplifier input signal.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: July 5, 2005
    Assignee: National Semiconductor Corporation
    Inventors: James T. Doyle, Dragan Maksimovic, Yushan Li
  • Patent number: 6900697
    Abstract: A method for providing power management in a radio frequency power amplifier is provided. An input voltage is received. A digital power supply signal is generated. From the input voltage, a regulated power supply signal is generated based on the digital power supply signal.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: May 31, 2005
    Assignee: National Semiconductor Corporation
    Inventors: James T. Doyle, Dragan Maksimovic, Yushan Li
  • Publication number: 20050062482
    Abstract: A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.
    Type: Application
    Filed: September 18, 2003
    Publication date: March 24, 2005
    Applicant: The Regents Of The University Of Colorado, a body corporate
    Inventors: Michael Vincent, Dragan Maksimovic
  • Patent number: 6868503
    Abstract: There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a critical path in the digital processing component is determined by a level of a power supply, VDD, of the digital processing component. The adjustable power supply is capable of supplying VDD to the digital processing component. The power supply adjustment circuitry is operable to receive a first selected clock signal and adjusts the level of VDD such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first selected clock signal and a second clock edge of the first selected clock signal immediately following the first clock edge.
    Type: Grant
    Filed: January 19, 2002
    Date of Patent: March 15, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Dragan Maksimovic, Sandeep Dhar, Bruno Kranzen, Ravindra Ambatipudi
  • Publication number: 20040049703
    Abstract: A method for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system is provided that includes providing a nominal power supply voltage to the system as a power supply voltage. A regulator clock signal is propagated through a delay line. The delay line comprises a plurality of delay cells and is operable to function based on the nominal power supply voltage. A plurality of pairs of delay cells are sampled until a first and second delay cell are identified based on the first delay cell receiving the regulator clock signal and the second delay cell failing to receive the regulator clock signal at a specified time. A reference voltage is provided to the system as the power supply voltage. The system is operated using the first and second delay cells to determine whether to adjust the power supply voltage for the system.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Applicant: National Semiconductor Corporation
    Inventors: Dragan Maksimovic, Sandeep Dhar
  • Publication number: 20030093160
    Abstract: Apparatus for efficiently supplying energy to a device in a circuit, the apparatus comprising a powered device having a critical path delay; delay line operative to model said critical path delay; control logic responsive to output from said delay line and operative to generate control output; and a power converter operative to adjust supply voltage to said powered device in response to said generated control output, wherein the delay line, the control logic, and the power converter cooperate to provide first order bang-bang control of said critical path delay.
    Type: Application
    Filed: November 8, 2002
    Publication date: May 15, 2003
    Applicant: The Regents Of The University Of Colorado, a body corporate
    Inventors: Dragan Maksimovic, Sandeep C. Dhar
  • Patent number: 6548991
    Abstract: There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.
    Type: Grant
    Filed: January 19, 2002
    Date of Patent: April 15, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Dragan Maksimovic, Sandeep Dhar, Ravindra Ambatipudi, Bruno Kranzen
  • Patent number: 5867379
    Abstract: This patent disclosure describes new non-linear carrier-pulse-width modulators for control of high power-factor boost rectifiers. In the new modulators, the switch duty ratio is determined by comparing a signal derived from the main switch current with a periodic, nonlinear carrier signal .nu..sub.c (t, .nu..sub.m). The shape of the carrier is selected so that the resulting input current follows the input voltage, as required for unity-power-factor rectification. A slowly-varying modulating input .nu..sub.m can be used to adjust the power level and to regulate the output dc voltage. The controller based on the new non-linear-carrier modulator has a number of advantageous properties: sensing of the input line voltage is eliminated; for current shaping, only sensing of the power switch current is needed; current shaping does not require an error amplifier with feedback loop compensation; the multiplier in the voltage feedback loop is eliminated; and the converter operates in the continuous conduction mode.
    Type: Grant
    Filed: January 12, 1995
    Date of Patent: February 2, 1999
    Assignee: University of Colorado
    Inventors: Dragan Maksimovic, Robert W. Erickson, Yungtaek Jang
  • Patent number: 5383109
    Abstract: A power supply for providing a single level dc output voltage, with input power factor correction, from a wide range of ac input voltages commonly available worldwide. The power supply rectifier circuit can be configured as a full wave bridge for high line voltage inputs and as a voltage doubler for low voltage inputs. Output voltage regulation and power factor correction are accomplished by a high frequency boost circuit having two inductors connected in parallel for the low input voltage configuration and in series for the high input voltage configuration. The high frequency switching semiconductor components are connected in a series circuit which limits their voltage requirement to one-half the output voltage.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: January 17, 1995
    Assignee: University of Colorado
    Inventors: Dragan Maksimovic, Robert W. Erickson