Abstract: A memory module having balanced data input/output contacts. A memory module includes a printed circuit board having an edge connector and a plurality of memory integrated circuits. The edge connector may be adapted for insertion into a socket of a motherboard of a computer system, for example. The edge connector includes a plurality of contact pads on both sides of the printed circuit board. The contact pads are configured to convey data signals, power and ground to and from the printed circuit board. The power and ground contact pads alternate along the edge connector. There are no more than four data signal contact pads without intervening power or ground contact pads.

Abstract: A memory module comprising a printed circuit board having mounting locations for a plurality of memory chips. A line driver having a plurality of outputs for each input is used to drive address and control signals to the chips, with each set of outputs coupled to a subset of the chips. Memory access time is improved by limiting subset size and thereby limiting driver loading. Subsets may correlate to banks of memory chips. Access time is substantially the same for a module with a plurality of banks of memory chips as it is for a module with only one bank of chips. Computer memory may be efficiently exchanged by using only such memory modules, allowing higher clock speed since the range of memory access times is reduced and requiring no change to system memory configuration or settings. Memory modules having differing capacities can be easily interchanged in the system.

Abstract: An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.

Abstract: A computer system which may allow a centerplaneless design. The computer system may include various client circuit boards including processor circuit boards, memory circuit boards and switch circuit boards. The processor circuit boards may each include at least one processor, while the memory circuit boards may each include memory which is accessible by each processor. The switch circuit boards may include a plurality of detachable connectors for interconnecting each of the processor circuit boards to each of the memory circuit boards. At least one of the switch circuit boards may convey redundant memory access information. Each of the boards may be hot swappable.

Abstract: A computer system employing redundant cooling fans. A system includes a first and a second array of circuit boards and a first and a second cooling fan. The two arrays of circuit boards are positioned such that the first array of circuit boards is substantially perpendicular to the second array of circuit boards. The first fan is positioned close to the first array of circuit boards and the second fan is positioned close to the second array of circuit boards. The first fan is positioned to force intake air across the first and the second arrays of circuit boards and the second fan is positioned to exhaust the forced intake air after it passes over the second array of circuit boards. Each of the fans may be hot swappable.

Abstract: A memory subsystem including error correction. A memory subsystem includes a memory controller and system memory including a plurality of memory modules. The system memory may be coupled to the memory controller by a memory interconnect. Each of the plurality of memory modules includes a circuit board and a plurality of memory chips mounted to the circuit board. The memory controller may store portions of a data segment across at least two of the memory modules. The memory controller may further store parity of the portions of the data segment in a corresponding location of another of the memory modules.

Abstract: A computer system employing redundant power distribution. A computer system includes power distribution boards arranged to distribute power such that the computer system may continue to operate if there is any single point of power failure. The computer system includes a first plurality of circuit boards, a plurality of switch circuit boards and a first and second power distribution board. The plurality of switch circuit boards may be coupled to the first plurality of circuit boards and may convey address and data information between the first plurality of circuit boards. The first power distribution board and the second power distribution board may be coupled to independently distribute power to each of the first plurality of circuit boards. At least two of the first plurality of circuit boards may be coupled to independently distribute power to each of the plurality of switch circuit boards.

Abstract: Circuit board orientation in a computer system. A system includes a first set of circuit boards and a second set of circuit boards. The first set of circuit boards may be mated via a first and second set of connectors to the second set of circuit boards such that the first set of circuit boards is oriented substantially orthogonal with respect to the second set of circuit boards. Each of the boards may be accessible and hot swappable.

Abstract: A high-performance memory module. The memory module is designed for a computer system with a wide data path. The memory module is implemented using a small printed circuit board (PCB), with a plurality of memory chips and a connector mounted upon the PCB. Signal traces for control, address, and data signals are arranged in such a manner as to minimize the length of each signal trace, thereby saving PCB area. On the connector, an electrical ground pin is located between each pair of signal pins, which may allow for a low-resistance return current path, and may therefore allow the module to operate at higher clock frequencies. Furthermore, locating a ground pin between each pair of signal pins may help reduce signal interference, or “crosstalk”, thereby improving signal integrity of the memory module.

Abstract: A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended “regenerated” clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit.

Abstract: A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Abstract: A digital communication system is presented implementing a data transmission method which allows each of a pair of communication devices coupled to a transmission line to both transmit and receive data during each cycle of a clock signal (i.e., simultaneous bidirectional data transmission). The digital communication system includes a first and second communication devices coupled to opposite ends of a transmission line. Both the first and second communication devices operate in response to a periodic clock signal. The first and second communication devices simultaneously: (i) drive an output data signal upon the transmission line during a first portion of a period of the clock signal, and (ii) receive an input signal from the transmission line during a remainder of the period of the clock signal. The communication devices may be coupled to receive the clock signal via a clock signal line, or may include circuitry to generate and synchronize two separate clock signals.

Abstract: An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.

Abstract: A memory module for expanding memory of a computer. The memory module comprises a printed circuit board including a connector edge having a plurality of contact pads configured to convey data signals, power and ground to and from said printed circuit board. The power and ground contact pads alternate along said connector edge with no more than four adjacent data signal contact pads without intervening power or ground contact pads. A plurality of memory devices mounted on the printed circuit board. A clock driver is coupled to each of the plurality of memory devices and is configured to receive a differential clock signal and to produce at least one single-ended clock signal for clocking the plurality of memory devices. The clock driver includes a phase-locked loop for phase-locking the at least one single-ended clock signal.

Abstract: A memory module comprising a printed circuit board having mounting locations for a plurality of memory chips. A line driver having a plurality of outputs for each input is used to drive address and control signals to the chips, with each set of outputs coupled to a subset of the chips. Memory access time is improved by limiting subset size and thereby limiting driver loading. Subsets may correlate to banks of memory chips. Access time is substantially the same for a module with a plurality of banks of memory chips as it is for a module with only one bank of chips. Computer memory may be efficiently exchanged by using only such memory modules, allowing higher clock speed since the range of memory access times is reduced and requiring no change to system memory configuration or settings. Memory modules having differing capacities can be easily interchanged in the system.

Abstract: An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.

Abstract: An optical receiver for receiving a first input data signal and a second input data signal, the optical receiver comprising: a first photo-detector, the first photo-detector operable to receive the first input data signal and operable to output a first electrical signal; a second photo-detector, the second photo-detector operable to receive the second input data signal and operable to output a second electrical signal; a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive the first electrical signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; and a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first electrical signal and the second electrical signal.

Abstract: A system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. Switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic selects either the first clock signal or the second clock signal as a local clock signal. The switching logic further monitors the first clock signal for a failure. If a failure is monitored, the switching logic accepts the second clock signal as the local clock signal in place of the first clock signal. One or more clock local loads operate according to the local clock signal. The switching logic may control the input to a phase locked loop (PLL) that provides the local clock signal to the local clock loads. The method includes a PLL synchronizing an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing.

Abstract: A memory module having balanced data input/output contacts. A memory module includes a printed circuit board having an edge connector and a plurality of memory integrated circuits. The edge connector may be adapted for insertion into a socket of a motherboard of a computer system, for example. The edge connector includes a plurality of contact pads on both sides of the printed circuit board. The contact pads are configured to convey data signals, power and ground to and from the printed circuit board. The power and ground contact pads alternate along the edge connector. There are no more than four data signal contact pads without intervening power or ground contact pads.

Abstract: A digital communication system is presented including at least one transmission line coupled between a first and second communication devices and used to convey binary data from the first communication device to the second communication device. A termination resistor and one end of the transmission line are coupled to an input node of the second communication device. An electrical voltage level existing at the input node of the second communication device may be substantially dependent upon an amount of electrical current flowing through the termination resistor. The termination resistor may have a value substantially equal to a characteristic impedance of the transmission line such that signal reflections and distortion occurring within the transmission line are substantially reduced. Three or more different voltage levels may be present upon the transmission line dependent upon the binary data.