Patents by Inventor Dror Avni
Dror Avni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10113170Abstract: The present invention relates to methods of treating, preventing, reducing the severity of, reducing the incidence of, delaying the onset of, or reducing pathogenesis of an inflammatory skin disease, condition or lesion in a human subject, which include the step of administering to the subject a therapeutically effective amount of mi RNA compositions. In addition, methods of this invention may be used to treat symptoms of inflammatory skin diseases and reduce and/or inhibit keratinocyte proliferation.Type: GrantFiled: July 23, 2015Date of Patent: October 30, 2018Assignee: TEL HASHOMER MEDICAL RESEARCH INFRASTRUCTURE AND SERVICES LTD.Inventors: Yechezkel Sidi, Dror Avni, Gali Lerman
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Publication number: 20170335328Abstract: The present invention relates to methods of treating, preventing, reducing the severity of, reducing the incidence of, delaying the onset of, or reducing pathogenesis of an inflammatory skin disease, condition or lesion in a human subject, which include the step of administering to the subject a therapeutically effective amount of mi RNA compositions. In addition, methods of this invention may be used to treat symptoms of inflammatory skin diseases and reduce and/or inhibit keratinocyte proliferation.Type: ApplicationFiled: July 23, 2015Publication date: November 23, 2017Applicant: TEL HASHOMER MEDICAL RESEARCH INFRASTRUCTURE AND SERVICES LTD.Inventors: Yechezkel SIDI, Dror AVNI, Gali LERMAN
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Publication number: 20100146239Abstract: The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and writing algorithms are presented.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Applicant: Infinite Memories Ltd.Inventors: Amir GABAI, Yoav Yogev, Dror Avni, Eli Lusky
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Patent number: 7420848Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.Type: GrantFiled: January 9, 2006Date of Patent: September 2, 2008Assignee: Saifun Semiconductors Ltd.Inventors: Assaf Shappir, Dror Avni, Boaz Eitan
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Patent number: 7079420Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.Type: GrantFiled: December 30, 2003Date of Patent: July 18, 2006Assignee: Saifun Semiconductors Ltd.Inventors: Assaf Shappir, Dror Avni, Boaz Eitan
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Publication number: 20060126396Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.Type: ApplicationFiled: January 9, 2006Publication date: June 15, 2006Applicant: Saifun Semiconductors, Ltd.Inventors: Assaf Shappir, Dror Avni, Boaz Eitan
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Patent number: 6937521Abstract: A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit.Type: GrantFiled: May 28, 2002Date of Patent: August 30, 2005Assignee: Saifun Semiconductors Ltd.Inventors: Dror Avni, Boaz Eitan
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Patent number: 6928001Abstract: A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit.Type: GrantFiled: December 7, 2000Date of Patent: August 9, 2005Assignee: Saifun Semiconductors Ltd.Inventors: Dror Avni, Boaz Eitan
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Publication number: 20050058005Abstract: A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.Type: ApplicationFiled: December 30, 2003Publication date: March 17, 2005Inventors: Assaf Shappir, Dror Avni, Boaz Eitan
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Publication number: 20040222437Abstract: A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit.Type: ApplicationFiled: December 7, 2000Publication date: November 11, 2004Inventors: Dror Avni, Boaz Eitan
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Patent number: 6700818Abstract: A method for operating bits of memory cells in a memory array, the method including applying operating pulses to bits of a sample of memory cells, determining a response of at least one of an electrical, physical and mechanical property (e.g., threshold voltage) of the bits to the operating pulses, and applying at least one further operating pulse to the rest of the array, the at least one further operating pulse being a function of the response.Type: GrantFiled: August 5, 2002Date of Patent: March 2, 2004Assignee: Saifun Semiconductors Ltd.Inventors: Assaf Shappir, Dror Avni, Boaz Eitan
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Publication number: 20030156456Abstract: A method for operating bits of memory cells in a memory array, the method including applying operating pulses to bits of a sample of memory cells, determining a response of at least one of an electrical, physical and mechanical property (e.g., threshold voltage) of the bits to the operating pulses, and applying at least one further operating pulse to the rest of the array, the at least one further operating pulse being a function of the response.Type: ApplicationFiled: August 5, 2002Publication date: August 21, 2003Inventors: Assaf Shappir, Dror Avni, Boaz Eitan
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Publication number: 20030002345Abstract: A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit.Type: ApplicationFiled: May 28, 2002Publication date: January 2, 2003Inventors: Dror Avni, Boaz Eitan
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Patent number: 5655125Abstract: A power conservation apparatus in a computer system. This apparatus includes an identification register in a processor comprising a contents including a plurality of flags for identifying the characteristics of the processor. One of these characteristics may be whether the processor includes static logic devices. In such systems, the clock connected to the processor may be halted, without the corruption of data in the processor. Other characteristics may include whether the processor is clocked at the same rate as the system, or whether the processor may operate on a lower voltage power source. The apparatus further comprises a transmission circuit for transferring the contents of the identification register from the processor to a system coupled to the processor upon the receipt of a first code.Type: GrantFiled: November 1, 1995Date of Patent: August 5, 1997Assignee: Intel CorporationInventors: Philip L. Cloud, Dror Avni
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Patent number: 5493683Abstract: A power conversation apparatus in a computer system. This apparatus includes an identification register in a processor comprising a contents including a plurality of flags for identifying the characteristics of the processor. One of these characteristics may be whether the processor includes static logic devices. In such systems, the clock connected to the processor may be halted, without the corruption of data in the processor. Other characteristics may include whether the processor is clocked at the same rate as the system, or whether the processor may operate on a lower voltage power source. The apparatus further comprises a transmission circuit for transferring the contents of the identification register from the processor to a system coupled to the processor upon the receipt of a first code.Type: GrantFiled: December 29, 1992Date of Patent: February 20, 1996Assignee: Intel CorporationInventors: Philip L. Cloud, Dror Avni
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Patent number: 5488639Abstract: A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first enable line, to the second sampling circuit by a second enable line, and to the third sampling circuit by a third enable line. The first, second, and third sampling circuits are coupled to receive the asynchronous signal. The selecting circuit is coupled to receive the output signals of the first, second and third sampling circuits. For the first sampling circuit, the following steps are performed: sampling the asynchronous signal, generating an output signal for the sampling circuit, waiting a period of time, and selecting the sampling circuit's output signal. These steps are also performed for the second sampling circuit and the third sampling circuit.Type: GrantFiled: December 21, 1993Date of Patent: January 30, 1996Assignee: Intel CorporationInventors: Peter D. MacWilliams, Dror Avni, Avi Liebermensch, Anan Baransy, Robert L. Farrell
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Patent number: 5304872Abstract: A dual mode input buffer having two modes of operation, a first mode of operation which provides a first CMOS level output from a TTL level input while operating at a first voltage level, and a second mode of operation which provides a second CMOS level output from a TTL level input while operating at a second voltage level. A first input provides TTl level inputs. An output provides a first CMOS level output and a second CMOS level output, one at at a time, depending on the mode of operation. A second input selects one of the two operation modes. Buffer means provides buffering of the signals provided on the first input. The buffer means has a level shifting transistor. Trip point level shifting means is provided for maintaining the trip point of the dual mode input buffer at approximately the same voltage level when the dual mode input buffer is operated at the second voltage level as when it operates at the first voltage level. A second input activates said trip point level shifting means.Type: GrantFiled: August 10, 1992Date of Patent: April 19, 1994Assignee: Intel CorporationInventors: Avi Avraham, Dror Avni, Daniel G. Genossar