Abstract: Non-standard sector size system support for SSD testing. An automated test equipment for simultaneous testing of multiple solid state drives (SSDs), wherein the SSD has a sector size that is not an integral power of two, includes a tester block configured to receive a command to read and verify an amount of data from the SSD starting at a starting address. The starting address is not constrained to correspond to a sector boundary and the amount of data is not constrained to be an integral multiple of the SSD data sector size. The test equipment also includes logic within said tester block configured to determine a starting sector of the SSD that the starting address points to, and logic within said tester block configured to determine a number of sectors required for the amount of data to be read. The tester block is configured to read a sector from the SSD.

Abstract: Fast Address to Sector Number/Offset Translation to Support Odd Sector Size Testing. A machine-implemented method of determining a sector number from a given address for testing a solid state drive (SSD), wherein the SSD sector size is not an integral power of 2, includes determining an approximate sector size as the closest power of 2 less than the sector size and determining an error factor as the ratio of the approximate sector size divided by the sector size. The method also includes forming the sector number by shifting the address right by the base 2 logarithm of the approximate sector size.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments enable efficient and effective random generation of test input information. In one embodiment a method includes accessing a plurality of data values to write to a DUT, generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values, wherein assignments of a particular address to different respective ones of the data values are randomly repeatable; and directing writing of the data values to the DUT in accordance with the plurality of addresses that are randomly generated and randomly repeated. The generating a plurality of addresses randomly can include normalization. Generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values can include performing a confirmation check.

Abstract: An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

Abstract: An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.

Abstract: A method for testing using an automated test equipment (ATE) comprises transmitting instructions for executing tests on a device under test (DUT) from a tester processor to a queue communicatively coupled with the tester processor and a Field Programmable Gate Array (FPGA), wherein the tester processor is configured to determine a hardware acceleration mode from a plurality of hardware acceleration modes for executing tests on the DUT. Further, the hardware acceleration mode is configured to distribute functionality for generating commands and data between the tester processor and the FPGA, wherein in at least one hardware acceleration mode the tester processor is configured to generate commands for testing the DUT and the FPGA is configured to generate data for testing the DUT. The method also comprises accessing the instructions in the queue, translating the instructions into commands associated with testing the DUT and transmitting the commands to the DUT.

Abstract: A method for monitoring a communication link between a device under test (DUT) and automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a DUT using a protocol analyzer module, wherein the data traffic comprises a flow of traffic between the DUT and a protocol core of a programmable logic device, wherein the protocol analyzer module is integrated within the programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, and wherein the protocol core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method further comprises saving results associated with the monitoring in a memory associated with the protocol analyzer module and transmitting the results upon request to an application program executing on the system controller.

Abstract: A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.

Abstract: Fast parallel CRC determination to support SSD testing includes a test data pattern generator for generating test data for storage onto a memory storage device under test (DUT), wherein the generator is operable to generate, every clock cycle, a respective N bit word comprising a plurality of M bit subwords, a digest circuit operable to employ a digest function on each N bit word to produce, every clock cycle, a respective word digest for each N bit word, and a storage circuit operable to store each N bit word along with an associated word digest to the DUT.

Abstract: Non-standard sector size system support for SSD testing. An automated test equipment for simultaneous testing of multiple solid state drives (SSDs), wherein the SSD has a sector size that is not an integral power of two, includes a tester block configured to receive a command to read and verify an amount of data from the SSD starting at a starting address. The starting address is not constrained to correspond to a sector boundary and the amount of data is not constrained to be an integral multiple of the SSD data sector size. The test equipment also includes logic within said tester block configured to determine a starting sector of the SSD that the starting address points to, and logic within said tester block configured to determine a number of sectors required for the amount of data to be read. The tester block is configured to read a sector from the SSD.

Abstract: Fast Address to Sector Number/Offset Translation to Support Odd Sector Size Testing. A machine-implemented method of determining a sector number from a given address for testing a solid state drive (SSD), wherein the SSD sector size is not an integral power of 2, includes determining an approximate sector size as the closest power of 2 less than the sector size and determining an error factor as the ratio of the approximate sector size divided by the sector size. The method also includes forming the sector number by shifting the address right by the base 2 logarithm of the approximate sector size.

Abstract: A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.

Abstract: A method for monitoring a communication link between a device under test (DUT) and automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a DUT using a protocol analyzer module, wherein the data traffic comprises a flow of traffic between the DUT and a protocol core of a programmable logic device, wherein the protocol analyzer module is integrated within the programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, and wherein the protocol core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method further comprises saving results associated with the monitoring in a memory associated with the protocol analyzer module and transmitting the results upon request to an application program executing on the system controller.

Abstract: A method for diagnosing a root cause of failure using automated test equipment (ATE) is disclosed. The method comprises identifying a failing device under test (DUT). Further, the method comprises opening a test program log associated with the failing DUT and determining a time of failure by parsing through the test program log to find an identifier and timestamp associated with the failure. Finally, the method comprises displaying the test program log in a window within a graphical user interface, wherein a relevant section of the test program log associated with the failure is displayed in the window.

Abstract: An automated test equipment for simultaneous testing of multiple devices includes a traffic capture circuit configured to capture communications with a device under test, a capture memory configured to store the communications captured by the traffic capture circuit, and a routing logic configured to read the communications from the capture memory, e.g., random access memory (RAM). There may be one of each of the traffic capture circuit, the capture RAM, and the routing logic for each device of the multiple devices.

Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Abstract: Real-time capture of traffic upon failure for protocol debug. In accordance with an embodiment of the present invention, an automated test equipment for simultaneous testing of multiple devices includes a traffic capture circuit configured to capture communications with a device under test, a capture memory configured to store the communications captured by the traffic capture circuit, and a routing logic configured to read the communications from the capture memory, e.g., random access memory (RAM). There may be one of each of the traffic capture circuit, the capture RAM, and the routing logic for each device of the multiple devices.

Abstract: An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

Abstract: An integrated circuit (IC) tester includes a set of nodes providing test access to separate terminals of an IC and each carrying out a sequence of actions at the terminal in response to test vector sequences. Each node includes a low speed vector memory supplying test vectors during the test. A host writes vectors into the vector memories before the test sending them over a common bus to vector write caches within each node. The write caches compensate for access speed limitations of the vector memory. During the test, blocks of vectors are read out of the vector memory at a low rate and written into a high speed read cache array. An instruction processor within each node reads individual vectors read out of the read cache array at a high rate and uses them for controlling test operations at the node during each cycle of the test.