Abstract: An integrated circuit (IC) tester includes a master controller and a set of tester nodes. Each tester node includes a vector memory controller, a vector memory, and a pin electronics circuit. During a test the pin electronics circuit carries out the sequence of actions in response to a sequence of vectors produced by the vector memory controller. To prepare for a test, a separate set of vectors is written into each vector memory. The vector memory controller thereafter moves blocks of vectors from the vector memory as needed to an internal vector cache. During the test, the master controller sends the same sequence of instructions concurrently to each vector memory controller. Each vector memory controller executes each instruction of the sequence by generating and supplying an address to the vector cache. The vector cache responds by reading out an addressed test vector and supplying it to the pin electronics circuit.

Abstract: An integrated circuit (IC) tester employs both central and distributed data sources for controlling tester operation during a test. The tester includes a master controller, a central scan data source, and a set of tester nodes. Each tester node carries out a sequence of test actions at an IC terminal, each action being defined by a data word (test vector). Before the test sets of vectors are written into vector memories in the nodes and separate control data is loaded into registers in each node. During the test, the scan data source sends scan data words concurrently to all tester nodes, and each node stores them. The master controller sends a similar instruction to each tester node during each cycle of the test. Some instructions reference a vector stored in the node and instruct all tester nodes to carry out the action indicated by the referenced vector.

Abstract: An integrated circuit tester includes a node for each terminal of a device under test. Each node includes a pin electronics circuit for carrying out test activities at the device terminal and a vector memory system for supplying a vector sequence to the local pin electronics circuit for controlling its test activities. To program the tester, a host computer transmits an appropriate set of vectors to each vector memory system via a common bus. Before sending vectors to the vector memory systems, the host computer sends them control data assigning each to one or more "virtual channels" such that all vector memory systems that are to receive a similar set of vectors are assigned to a similar virtual channel. Also, before transmitting each set of vectors on the bus, the host computer broadcasts additional control data to all vector memory systems designating one virtual channel as active. Thereafter only those vector memory systems assigned to the active virtual channel accept the transmitted vector set.