Patents by Inventor Duan Quan Liao
Duan Quan Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10153289Abstract: A non-volatile memory including a substrate, a charge storage structure, two metal gate structures, a first dielectric layer, a second dielectric layer, a first doped region and a second doped region is provided. The charge storage structure is disposed on the substrate. The metal gate structures are disposed on the substrate at two sides of the charge storage structure. The first dielectric layer is disposed between the charge storage structure and the metal gate structures. The second dielectric layer is disposed between the charge storage structure and the substrate. The first doped region and the second doped region are disposed in the substrate at sides of the metal gate structures away from the charge storage structure.Type: GrantFiled: February 25, 2016Date of Patent: December 11, 2018Assignee: United Microelectronics Corp.Inventors: Ji-Ye Li, Duan-Quan Liao
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Patent number: 9941161Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.Type: GrantFiled: August 28, 2015Date of Patent: April 10, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, Ching Hwa Tey
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Publication number: 20170213838Abstract: A non-volatile memory including a substrate, a charge storage structure, two metal gate structures, a first dielectric layer, a second dielectric layer, a first doped region and a second doped region is provided. The charge storage structure is disposed on the substrate. The metal gate structures are disposed on the substrate at two sides of the charge storage structure. The first dielectric layer is disposed between the charge storage structure and the metal gate structures. The second dielectric layer is disposed between the charge storage structure and the substrate. The first doped region and the second doped region are disposed in the substrate at sides of the metal gate structures away from the charge storage structure.Type: ApplicationFiled: February 25, 2016Publication date: July 27, 2017Inventors: Ji-Ye Li, Duan-Quan Liao
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Patent number: 9698229Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.Type: GrantFiled: January 17, 2012Date of Patent: July 4, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, Ching-Hwa Tey, Xiao Zhong Zhu
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Publication number: 20170162450Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Duan Quan Liao, Yikun Chen, Ching-Hwa Tey, Xiao Zhong Zhu
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Publication number: 20170117150Abstract: A semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.Type: ApplicationFiled: January 8, 2017Publication date: April 27, 2017Inventors: Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Patent number: 9583594Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.Type: GrantFiled: August 19, 2015Date of Patent: February 28, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, Ching Hwa Tey
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Publication number: 20170040179Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.Type: ApplicationFiled: August 28, 2015Publication date: February 9, 2017Inventors: Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Publication number: 20170025519Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.Type: ApplicationFiled: August 19, 2015Publication date: January 26, 2017Inventors: Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Patent number: 9401280Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.Type: GrantFiled: May 28, 2014Date of Patent: July 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Wei Cheng, Yikun Chen, Ching Hwa Tey, Xiao Zhong Zhu
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Patent number: 9385193Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.Type: GrantFiled: May 27, 2014Date of Patent: July 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu
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Patent number: 9331200Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure. Preferably, the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn.Type: GrantFiled: January 6, 2015Date of Patent: May 3, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Lanxiang Wang, Hong Liao, Chao Jiang, Duan Quan Liao, Ye Chao Li
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Patent number: 9276057Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.Type: GrantFiled: January 27, 2014Date of Patent: March 1, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, Ching Hwa Tey, Xiao Zhong Zhu
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Publication number: 20150348789Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Wei Cheng, Yikun Chen, CHING HWA TEY, Xiao Zhong Zhu
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Publication number: 20150214293Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.Type: ApplicationFiled: January 27, 2014Publication date: July 30, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Duan Quan Liao, Yikun Chen, CHING HWA TEY, Xiao Zhong Zhu
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Publication number: 20150140778Abstract: A method for manufacturing the MIM capacitor structure is provided. A first damascene electrode layer is formed in the first opening formed in a first dielectric layer. An insulating barrier layer is formed to cover the first dielectric layer and the first damascene electrode layer. A second opening and a third opening are formed in the second dielectric layer formed on the insulating barrier layer. The second opening and the third opening are located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom. The insulating barrier layer in the third opening is removed to expose a portion of the first damascene electrode layer. A second damascene electrode layer is formed in the second opening to be contacted with the insulating barrier layer and a dual damascene structure is formed in the third opening to be contacted with the first damascene electrode layer.Type: ApplicationFiled: December 22, 2014Publication date: May 21, 2015Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: JI FENG, DUAN-QUAN LIAO, HAI-LONG GU, YING-TU CHEN
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Publication number: 20150140800Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei Cheng, Ming Sheng Xu, Duan Quan Liao, Yikun Chen, CHING HWA TEY
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Patent number: 9023726Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.Type: GrantFiled: November 18, 2013Date of Patent: May 5, 2015Assignee: United Microelectronics Corp.Inventors: Wei Cheng, Ming Sheng Xu, Duan Quan Liao, Yikun Chen, Ching Hwa Tey
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Patent number: 8946854Abstract: A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.Type: GrantFiled: November 9, 2011Date of Patent: February 3, 2015Assignee: United Microelectronics CorporationInventors: Ji Feng, Duan-Quan Liao, Hai-Long Gu, Ying-Tu Chen
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Publication number: 20140252482Abstract: A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure.Type: ApplicationFiled: May 27, 2014Publication date: September 11, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Rai-Min Huang, Sheng-Huei Dai, Chen-Hua Tsai, Duan Quan Liao, Yikun Chen, Xiao Zhong Zhu