SEMICONDUCTOR PROCESS
A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.
This application is a divisional application of and claims the benefit of U.S. patent application Ser. No. 13/351,231, filed Jan. 17, 2012.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates generally to a semiconductor structure and process thereof, and more specifically, to a semiconductor structure and process thereof, which directly forms an epitaxial structure in a contact hole.
2. Description of the Prior Art
Epitaxy technology is often used to form semiconductor components. The functions of the epitaxy technology are that not only can a whole single-crystalline silicon layer be formed but also problems caused in semiconductor processes can be solved. In addition, the epitaxy technology may also be used to form semiconductor components having particular functions. For instance, as a silicide process is performed, a metal layer will cover a source/drain region, so that metals in the metal layer will react with the silicon below. A silicide layer is thereby formed, which is used for electrically connecting the source/drain region (usually made of silicon or silicon compounds) below with the metal plug above as well as buffering the structural difference between both, thereby reducing sheet resistance. When silicon in the source/drain region over-reacts with the metal layer or the source/drain region is too shallow, however, the source/drain region will deplete after reacting, leading to a break down in the p-n junction. Thus, an improved method is provided, which forms an epitaxial layer before the metal layer is formed on the source/drain region. For example, epitaxial silicon or epitaxial silicon compounds can be paired with the silicon substrate. This means that the epitaxial layer located between the source/drain region and the metal layer can react with the metal layer without reducing the volume of the source/drain region.
For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to the very deep sub-micron era such as 65-nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue. In order to improve device performance, crystal strain technology has been developed. Crystal strain technology is becoming more and more attractive as a means for getting better performance in the field of MOS transistor fabrication. Forming an epitaxial layer on a source/drain region of a semiconductor crystal alters the speed at which charges move through the crystal. Strain makes MOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel.
As the size of a semiconductor component is scaled down, the method of forming the epitaxial layer on the source/drain region described above causes some negative effects. By using a fin-shaped field-effect transistor as an example, a source/drain region is formed in a fin-shaped structure, and an epitaxial structure covers the source/drain region. The epitaxial structure enlarges the volume of the fin-shaped structure, however, leading to a reduction of space between each fin-shaped structure. Even worse, this causes each adjacent fin-shaped structure to be merged together, giving rise to a short circuit of the semiconductor component. A way of preventing this short circuit is providing enough space between each fin-shaped structure; however, this would restrict the size of the semiconductor component and prevent the desired scaling down. The problem becomes particularly significant in a static random access memory (SRAM) having dense distribution of fin-shaped structures.
SUMMARY OF THE INVENTIONThe present invention provides a semiconductor structure and process thereof, which forms an epitaxial structure in a contact hole to solve the above problem.
The present invention provides a semiconductor structure including at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region.
The present invention further provides a semiconductor process including the following steps. A substrate is provided. A MOS transistor is formed on the substrate, wherein the MOS transistor includes a gate located on the substrate and a source/drain region located in the substrate next to the gate. An interdielectric layer covering the substrate next to the gate is formed. A plurality of contact holes are formed in the interdielectric layer and expose at least a part of the source/drain region. An epitaxial structure is respectively formed in each of these contact holes, directly contacts and is only located on the source/drain region. A silicide is formed on the epitaxial structure in each of these contact holes. A dielectric layer is deposited on the interdielectric layer and covers the gate. A plurality of corresponding contact holes is formed in the dielectric layer for connecting these contact holes. A metal material is respectively filled into each of these contact holes, their corresponding contact holes and on the silicide.
The present invention provides a semiconductor process including the following steps. A substrate is provided. A MOS transistor is formed on the substrate, wherein the MOS transistor includes a gate located on the substrate and a source/drain region located in the substrate next to the gate. An interdielectric layer and a dielectric layer covering the substrate next to the gate are sequentially formed. A plurality of contact holes is formed in the interdielectric layer and in the dielectric layer to expose at least a part of the source/drain region. An epitaxial structure is respectively formed in each of these contact holes. A silicide is respectively formed on the epitaxial structure in each of these contact holes. A metal material is respectively filled into these contact holes and on the silicide.
According to the above, the present invention provides a semiconductor structure and process thereof, which can control the growth area of the epitaxial structure by forming the epitaxial structure in these contact holes. For example, the size and the shape of the epitaxial structure can be controlled effectively. Therefore, the adjacent epitaxial structures will not merge together, which prevents short circuiting of a semiconductor component formed by the present invention. Also, the size of the semiconductor component can be scaled down by refining the layout of the semiconductor component.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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The present invention can also be applied to other semiconductor substrates. For example, a silicon-on-insulator substrate (not shown) is provided, and then a single crystalline silicon layer being a top part of the silicon-on-insulator substrate (not shown) is etched till an oxide layer being a middle part of the silicon-on-insulator substrate (not shown) is exposed, meaning the fin-shaped structure formed on the silicon-on-insulator substrate (not shown) is finished.
For clarifying the present invention, one fin-shaped structure 114 is depicted in this embodiment, but the present invention can also be applied to a plurality of fin-shaped structures 114.
A gate 120 covers the fin-shaped structure 114. The method of forming the gate 120 may include: a buffer layer (not shown), a gate dielectric layer (not shown), an electrode layer (not shown) and a cap layer (not shown) are sequentially formed and all are patterned, thereby a buffer layer 122 is formed on the fin-shaped structure 114, a gate dielectric layer 124 is formed on the buffer layer 122, an electrode layer 126 is formed on the gate dielectric layer 124 and a cap layer 128 is formed on the electrode layer 126. A spacer 129 is formed next to the buffer layer 122, the gate dielectric layer 124, the electrode layer 126 and the cap layer 128. Therefore, the manufacturing of the gate 120 is finished. Then, a source/drain region 130 is formed in the fin-shaped structure 114 next to the gate 120 by methods such as ion implantation process. The gate 120 and the source/drain region 130 constitute the MOS transistor M.
The buffer layer 122 may be a silicon dioxide layer; the gate dielectric layer 124 may be an oxide layer, a dielectric layer having a high dielectric constant, etc. The material of the dielectric layer having a high dielectric constant may be the group selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST); the electrode layer 126 may be a polysilicon layer; the cap layer 128 and the spacer 129 may be composed of silicon nitride, but are not limited thereto. In this embodiment, a gate last for high-K last process is applied, so that the gate dielectric layer 124 is a dielectric layer such as an oxide layer. Due to the electrode layer 126 being a polysilicon layer in this embodiment, the gate 120 is a polysilicon gate. In another embodiment, a gate Last for high-K first process, a gate first process, or a polysilicon gate process, etc. may be applied.
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Otherwise, the plurality of contact holes R and the gate contact hole (not shown) may be formed in the interdielectric layer 150 and the dielectric layer 190 at the same time by processes such as a photolithography process to expose at least a part of the source/drain region 130 and the low resistivity material 166. Then, the epitaxial structure 170 may be respectively formed in each of these contact holes R. Due to the low resistivity material 166 being metals, the epitaxial structure 170 will not formed thereon. The metal material (not shown) may be respectively filled into the contact holes R and the gate contact hole (not shown) and be planarized, at which point the semiconductor process of the present invention is finished.
A semiconductor structure can be formed by the first embodiment or by the second embodiment.
Above all, in the semiconductor processes of the first embodiment and the second embodiment, the epitaxial structure 170 are all formed in each of the contact holes R after the contact hole R are formed. Thus, the epitaxial structure 170 is restricted to be formed in the contact holes R. In this way, the growth area of the epitaxial structure 170 can be controlled, and thereby the epitaxial structure 170 on the fin-shaped structure 114 can be prevented from merging together. The size of the semiconductor structure 200 can also be scaled down by controlling the size and the shape of the epitaxial structure 170.
The semiconductor structure formed by the semiconductor processes of the first embodiment and the second embodiment can also be applied to various semiconductor devices. For example, the semiconductor structure can be applied to a static random access memory (SRAM). As the numbers of the MOS transistor of the semiconductor structure 200 are more than one, MOS transistors can be distributed to form a static random access memory (SRAM).
According to the above, the present invention provides a semiconductor structure and process thereof, which controls the growth area of an epitaxial structure by forming the epitaxial structure in each of the contact holes. Thus, the size and the shape of the epitaxial structure can be controlled. For example, in the process forming the semiconductor structure of the present invention, contact holes are formed and then an epitaxial layer is filled into each of the contact holes. More precisely, the method of forming these contact holes may include two steps: bottom contact holes are formed and the epitaxial layer and a silicide are filled into each of the bottom contact holes; then, top contact holes and a gate contact hole are formed. The method of forming these contact holes may also comprise one step only: the contact holes are formed at once; then an epitaxial layer, a silicide and a metal plug etc are sequentially formed into each of the contact holes.
Therefore, the growth area of the epitaxial structure in each of the contact holes can be controlled by applying the feature of the present invention, so each adjacent epitaxial structure can be prevented from merging together, which causes short circuits in a semiconductor component formed according to the prior art. Moreover, layout in the semiconductor component can be refined by the well-controlled growth area of epitaxial structures. As a result, the size of the semiconductor component can be scaled down.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A semiconductor process, comprising:
- providing a substrate;
- forming a MOS transistor on the substrate, wherein the MOS transistor comprises a gate located on the substrate and a source/drain region located in the substrate next to the gate;
- forming an interdielectric layer covering the substrate next to the gate;
- forming a plurality of contact holes in the interdielectric layer and exposing at least a part of the source/drain region;
- respectively forming an epitaxial structure in each of the contact holes, directly contacting and only located on the source/drain region;
- forming a silicide on the epitaxial structure in each of the contact holes;
- depositing a dielectric layer on the interdielectric layer and covering the gate;
- forming a plurality of corresponding contact holes in the dielectric layer and connecting the contact holes; and
- respectively filling a metal material into each of the contact holes and the corresponding contact holes and on the silicide.
2. The semiconductor process according to claim 1, wherein the gate comprises a polysilicon gate.
3. The semiconductor process according to claim 1, wherein the gate comprises a sacrificial gate, and further comprising:
- replacing the sacrificial gate with a metal gate after the interdielectric layer covering the substrate next to the gate is formed.
4. The semiconductor process according to claim 1, further comprising:
- forming a contact etch stop layer between the substrate and the interdielectric layer before the interdielectric layer covering the substrate next to the gate is formed.
5. The semiconductor process according to claim 1, wherein the substrate comprises a bulk substrate.
6. The semiconductor process according to claim 1, wherein the substrate comprises a bottom substrate and at least a fin-shaped structure on the bottom substrate, and the gate and the source/drain region are formed on the fin-shaped structure.
7. The semiconductor process according to claim 1, wherein the numbers of the MOS transistor are more than one, and the MOS transistors are distributed to form a static random access memory (SRAM).
8. The semiconductor process according to claim 1, wherein the epitaxial structure comprises a strained epitaxial silicon.
9. The semiconductor process according to claim 1, wherein respectively forming the epitaxial structure in each of the contact holes comprises respectively forming the epitaxial structure to fill up each of the contact holes.
10. The semiconductor process according to claim 1, wherein respectively forming the epitaxial structure in each of the contact holes comprises respectively forming the epitaxial structure to fill part of each of the contact holes.
11. The semiconductor process according to claim 1, further comprising:
- forming a gate contact hole in the dielectric layer to expose the gate while forming the plurality of corresponding contact holes in the dielectric layer.
12. A semiconductor process, comprising:
- providing a substrate;
- forming a MOS transistor on the substrate, wherein the MOS transistor comprises a gate located on the substrate and a source/drain region located on the substrate next to the gate;
- sequentially forming an interdielectric layer and a dielectric layer covering the gate and the substrate;
- forming a plurality of contact holes in the interdielectric layer and the dielectric layer to expose at least a part of the source/drain region;
- respectively forming an epitaxial structure in each of the contact holes;
- respectively forming a silicide on the epitaxial structure in each of the contact holes; and
- respectively filling a metal material into each of the contact holes and on the silicide.
13. The semiconductor process according to claim 12, wherein the gate comprises a polysilicon gate.
14. The semiconductor process according to claim 12, wherein the gate comprises a sacrificial gate, and the steps of sequentially forming an interdielectric layer and a dielectric layer covering the gate and the substrate comprise:
- forming the interdielectric layer on the substrate next to the sacrificial gate;
- replacing the sacrificial gate with a metal gate; and
- forming the dielectric layer on the interdielectric layer and covering the metal gate.
15. The semiconductor process according to claim 12, further comprising:
- forming a contact etch stop layer between the substrate and the interdielectric layer before the interdielectric layer and the dielectric layer covering the gate and the substrate are sequentially formed.
16. The semiconductor process according to claim 12, wherein the substrate comprises a bulk substrate.
17. The semiconductor process according to claim 12, wherein the substrate comprises a bottom substrate and at least a fin-shaped structure located on the bottom substrate, and the gate and the source/drain region are formed on the fin-shaped structure.
18. The semiconductor process according to claim 12, wherein the numbers of the MOS transistor are more than one, and the MOS transistors are distributed to forma static random access memory (SRAM).
19. The semiconductor process according to claim 12, wherein the epitaxial structure comprises a strained epitaxial silicon.
20. The semiconductor process according to claim 12, wherein respectively forming the epitaxial structure in each of the contact holes comprises respectively forming the epitaxial structure to fill up each of the contact holes.
21. The semiconductor process according to claim 12, wherein respectively forming the epitaxial structure in each of the contact holes comprises respectively forming the epitaxial structure to fill part of each of the contact holes.
22. The semiconductor process according to claim 12, further comprising:
- forming a gate contact hole in the dielectric layer to expose the gate while forming the plurality of contact holes.
Type: Application
Filed: Feb 16, 2017
Publication Date: Jun 8, 2017
Inventors: Duan Quan Liao (Singapore), Yikun Chen (Singapore), Ching-Hwa Tey (Singapore), Xiao Zhong Zhu (Singapore)
Application Number: 15/435,280