Patents by Inventor Duc Ho
Duc Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104164Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.Type: ApplicationFiled: December 13, 2022Publication date: March 28, 2024Inventors: HIEU VAN TRAN, STEPHEN TRINH, STANLEY HONG, THUAN VU, DUC NGUYEN, HIEN HO PHAM
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Publication number: 20190305832Abstract: A transmission protocol for a multi-way massive MIMO relay system uses linear processing, self-interference cancelation and successive cancelation decoding to significantly reduce the number of time-slots required for data exchange amongst user devices compared to that for the conventional data transmission protocol. As a result, the spectral efficiency of the system is significantly increased.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Inventors: Michail Matthaiou, Hien Quoc Ngo, Chung Duc Ho, Long Dinh Nguyen
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Patent number: 10127969Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.Type: GrantFiled: March 10, 2017Date of Patent: November 13, 2018Assignee: Micron Technology, Inc.Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
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Publication number: 20180094786Abstract: The invention introduces converging lenses connecting with optical fibers and a device for receiving sunlight that uses these lenses to converge sunlight from every angle of the sun during the day and the collected light beam at the output is quite parallel. To converge light from every angle of the sun, without using any motion part, small lenses are arranged to build a convex surface. Sunlight collected by these lenses become a parallel light beam and are guided by optical fibers. These optical fibers are arranged tightly to build a bundle of optical fibers in order to make it easier to further transmit and to use at the output of the device.Type: ApplicationFiled: October 12, 2017Publication date: April 5, 2018Applicant: University of Science, Vietnam National University - HanoiInventors: Thuat Tran Nguyen, Hieu Chi Hoang, Quan Duc Ho, Quan Quang Nguyen, Hai Hoang Nguyen
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Publication number: 20170186475Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.Type: ApplicationFiled: March 10, 2017Publication date: June 29, 2017Applicant: Micron Technology, Inc.Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
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Patent number: 9633713Abstract: Methods are disclosed. In an embodiment of one such method, a method of receiving command signals, the method comprises receiving command signals in combination with a signal provided to a memory address node at a first clock edge and a second clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge and the second clock edge of the clock signal, represents memory commands.Type: GrantFiled: March 7, 2016Date of Patent: April 25, 2017Assignee: Micron Technology, Inc.Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
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Publication number: 20160189763Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Applicant: Micron Technology, Inc.Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
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Patent number: 9281037Abstract: Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.Type: GrantFiled: May 7, 2010Date of Patent: March 8, 2016Assignee: Micron Technology, Inc.Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
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Publication number: 20100214864Abstract: Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.Type: ApplicationFiled: May 7, 2010Publication date: August 26, 2010Applicant: Micron Technology, Inc.Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
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Patent number: 7729191Abstract: Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.Type: GrantFiled: September 6, 2007Date of Patent: June 1, 2010Assignee: Micron Technology, Inc.Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
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Publication number: 20090067277Abstract: Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.Type: ApplicationFiled: September 6, 2007Publication date: March 12, 2009Applicant: Micron Technology, Inc.Inventors: Scott Smith, Duc Ho, J. Thomas Pawlowski
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Publication number: 20060262630Abstract: The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge circuit may be utilized to isolate the buses from each other and couple the buses together, depending on the control signals are received by the bridge circuit. As such, the bridge circuit enhances the operation of the memory device by reducing duplicative circuits and equalizing the voltage that are applied to the buses. In addition, the bridge circuit isolates the buses from each other to protect sensitive circuitry in the array and periphery circuitry from noise on the other bus.Type: ApplicationFiled: July 27, 2006Publication date: November 23, 2006Inventors: Duc Ho, Scott Smith
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Publication number: 20050201178Abstract: The present technique relates to a method and apparatus to provide a deep power down mode. In a memory device, such as DRAM or SRAM, various internal voltage buses provide power throughout the semiconductor chip. In a deep power down mode, grounding devices may be utilized to ground the internal voltage buses. With the internal voltage buses grounded, the outputs of the level shifters, which are control signals, may need to be forced into specific states. Through the use of the grounding devices and level shifters, leakage may be reduced and latch-up conditions may be reduced. As a result, the operation of the semiconductor chip may be enhanced because the problems associated with grounding the internal voltage buses may be diminished.Type: ApplicationFiled: March 10, 2004Publication date: September 15, 2005Inventors: Duc Ho, Scott Smith
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Publication number: 20050201183Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address.Type: ApplicationFiled: January 24, 2005Publication date: September 15, 2005Inventor: Duc Ho
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Publication number: 20050140349Abstract: The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge circuit may be utilized to isolate the buses from each other and couple the buses together, depending on the control signals are received by the bridge circuit. As such, the bridge circuit enhances the operation of the memory device by reducing duplicative circuits and equalizing the voltage that are applied to the buses. In addition, the bridge circuit isolates the buses from each other to protect sensitive circuitry in the array and periphery circuitry from noise on the other bus.Type: ApplicationFiled: December 31, 2003Publication date: June 30, 2005Inventors: Duc Ho, Scott Smith
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Patent number: 6826092Abstract: An improved predriver circuit for an output buffer is provided that can enable the output buffer to operate well within maximum and minimum IOL current specifications at lower internally regulated voltages. The predriver circuit comprises a limiter device configured to limit or otherwise regulate the maximum gate voltage provided to the gate of the pull-down transistor device. As a result, the pull-down transistor device can be sized optimally to provide additional margin to exceed the minimum IOL specification, while also improving the margin under the maximum IOL specification. The device is configured to limit the maximum gate voltage of the output pull-down transistor device to less than the maximum external power supply voltage.Type: GrantFiled: January 20, 2004Date of Patent: November 30, 2004Assignee: Micron Technology, Inc.Inventors: Duc Ho, Gary L. Howe
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Publication number: 20040150435Abstract: An improved predriver circuit for an output buffer is provided that can enable the output buffer to operate well within maximum and minimum IOL current specifications at lower internally regulated voltages. The predriver circuit comprises a limiter device configured to limit or otherwise regulate the maximum gate voltage provided to the gate of the pull-down transistor device. As a result, the pull-down transistor device can be sized optimally to provide additional margin to exceed the minimum IOL specification, while also improving the margin under the maximum IOL specification. The device is configured to limit the maximum gate voltage of the output pull-down transistor device to less than the maximum external power supply voltage.Type: ApplicationFiled: January 20, 2004Publication date: August 5, 2004Applicant: Micron Technology, Inc.Inventors: Duc Ho, Gary L. Howe
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Patent number: 6707722Abstract: An improved predriver circuit for an output buffer is provided that can enable the output buffer to operate well within maximum and minimum IOL current specifications at lower internally regulated voltages. The predriver circuit comprises a limiter device configured to limit or otherwise regulate the maximum gate voltage provided to the gate of the pull-down transistor device. As a result, the pull-down transistor device can be sized optimally to provide additional margin to exceed the minimum IOL specification, while also improving the margin under the maximum IOL specification. The device is configured to limit the maximum gate voltage of the output pull-down transistor device to less than the maximum external power supply voltage.Type: GrantFiled: July 23, 2002Date of Patent: March 16, 2004Assignee: Micron Technology, Inc.Inventors: Duc Ho, Gary L. Howe
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Publication number: 20040017696Abstract: An improved predriver circuit for an output buffer is provided that can enable the output buffer to operate well within maximum and minimum IOL current specifications at lower internally regulated voltages. The predriver circuit comprises a limiter device configured to limit or otherwise regulate the maximum gate voltage provided to the gate of the pull-down transistor device. As a result, the pull-down transistor device can be sized optimally to provide additional margin to exceed the minimum IOL specification, while also improving the margin under the maximum IOL specification. The device is configured to limit the maximum gate voltage of the output pull-down transistor device to less than the maximum external power supply voltage.Type: ApplicationFiled: July 23, 2002Publication date: January 29, 2004Applicant: Micron Technology, Inc.Inventors: Duc Ho Allen, Gary L. Howe
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Patent number: 6242936Abstract: A circuit (100) that drives word lines and tests a word line (102) in a semiconductor device is disclosed. A charge circuit (108) couples a supply voltage (VPP) to a charge node (106) according to a potential at a boot node (110). The charge node (106) supplies a charge voltage for the word line (102). In a standard cycle, the boot node (110) is charged to a high voltage, and maintained at the high potential, to keep the word line (102) charged. In a test cycle, the boot node (110) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (106) and the word line (102). In the event the word line (102) suffers from current leakage, a drop in potential will be detected at the charge rode (106).Type: GrantFiled: August 3, 1999Date of Patent: June 5, 2001Assignee: Texas Instruments IncorporatedInventors: Michael Duc Ho, Duy-Loan T. Le, Scott E. Smith