Abstract: A memory circuit is designed with a memory array (113, 115, 117, 119) having a plurality of banks. Each bank is addressable in response to a bank address signal (102), and each bank arranged in rows and columns of memory cells. Each of plural data leads (122) corresponds to a bank. Each data lead is selectively connected to a column of memory cells by a respective select transistor. A first decode circuit (501) has at least one input and one output terminal. The output terminal (525) is coupled to a control gate of at least one of the select transistors. Each of a plurality of second decode circuits (231) corresponds to a respective bank. Each second decode circuit has a memory element (423, 425, 428)), a plurality of input terminals and at least one output terminal. One second decode circuit input terminal (227) is coupled to receive a first address signal. Another second decode circuit input terminal (229) is coupled to receive the bank address signal.

Abstract: Switching circuits controlled by a fuse that can be blown after testing the DRAM part select the timing signals coupled from a binary counter to internal signal generator circuits. The internal Circuits control self refresh in this embodiment. The decision to leave the fuse intact or blow the fuse rests on the test results obtained from each part and can vary depending upon maturity of the manufacturing process, the pause test results obtained and whether a low power part is desired. The fuse is affected after fabrication of the chip and at the same time as other fuses used for redundancy. This provides another degree of freedom in the manufacture of integrated circuits.