Patents by Inventor Duc Pham
Duc Pham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8866520Abstract: One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.Type: GrantFiled: September 10, 2013Date of Patent: October 21, 2014Assignee: Altera CorporationInventors: Tien Duc Pham, Sergey Shumarayev, Richard G. Cliff
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Patent number: 8862966Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: GrantFiled: July 30, 2010Date of Patent: October 14, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Patent number: 8849742Abstract: A computer implemented method includes determining whether a time of day corresponds to a charging window, responsive to a determination that a vehicle is in a non-charging state. The method also includes retrieving a start time and charge requirement for an upcoming journey. The method further includes determining if sufficient time remains to charge a vehicle to the charge requirement, responsive to a determination that the time of day corresponds to the charging window. Also, the method includes alerting a user to the non-charging state, responsive to a determination that insufficient time remains to charge the vehicle to the charge requirement.Type: GrantFiled: January 24, 2012Date of Patent: September 30, 2014Assignee: Ford Global Technologies, LLCInventors: Karin Lovett, Beth Ann Dalrymple, David Hayes, Thanh Duc Pham, Jesus Cardoso, Darko Acevski
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Publication number: 20140211571Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.Type: ApplicationFiled: April 2, 2014Publication date: July 31, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Ming-Ju Edward LEE, Shadi M. BARAKAT, Warren Fritz KRUGER, Xiaoling XU, Toan Duc PHAM, Aaron John NYGREN
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Patent number: 8730758Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.Type: GrantFiled: June 24, 2009Date of Patent: May 20, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ju Edward Lee, Shadi M. Barakat, Warren Fritz Kruger, Xiaoling Xu, Toan Duc Pham, Aaron John Nygren
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Patent number: 8671304Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.Type: GrantFiled: July 30, 2010Date of Patent: March 11, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger
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Patent number: 8619931Abstract: Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.Type: GrantFiled: November 19, 2009Date of Patent: December 31, 2013Assignee: Altera CorporationInventors: Tien Duc Pham, Sergey Shumarayev, Tim Tri Hoang, Thungoc M. Tran, Vinh Van Ho, Leon Zheng
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Patent number: 8542042Abstract: One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.Type: GrantFiled: June 25, 2012Date of Patent: September 24, 2013Assignee: Altera CorporationInventors: Tien Duc Pham, Sergey Shumarayev, Richard G. Cliff
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Patent number: 8537956Abstract: A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.Type: GrantFiled: November 24, 2010Date of Patent: September 17, 2013Assignee: Altera CorporationInventors: Tien Duc Pham, Leon Zheng, Sergey Shumarayev, Zhi Y. Wong, Paul B. Ekas
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Publication number: 20130191321Abstract: A computer implemented method includes determining whether a time of day corresponds to a charging window, responsive to a determination that a vehicle is in a non-charging state. The method also includes retrieving a start time and charge requirement for an upcoming journey. The method further includes determining if sufficient time remains to charge a vehicle to the charge requirement, responsive to a determination that the time of day corresponds to the charging window. Also, the method includes alerting a user to the non-charging state, responsive to a determination that insufficient time remains to charge the vehicle to the charge requirement.Type: ApplicationFiled: January 24, 2012Publication date: July 25, 2013Applicant: Ford Global Technologies, LLCInventors: Karin Lovett, Beth Ann Dalrymple, David Hayes, Thanh Duc Pham, Jesus Cardoso, Darko Acevski
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Patent number: 8489912Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.Type: GrantFiled: July 30, 2010Date of Patent: July 16, 2013Assignee: ATI Technologies ULCInventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael John Litt
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Patent number: 8443225Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: GrantFiled: August 13, 2012Date of Patent: May 14, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Publication number: 20130096768Abstract: A computer-implemented method includes detecting a reportable change in vehicle state. The method also includes qualifying the reportable change for delivery based on evaluation of one or more situational variables associated with the reportable change. Further, the method includes delivering a notification relating to the reportable change to a wireless to be delivered to a device user despite an active do not disturb state of the wireless device, conditional on the qualification of the reportable change as deliverable.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Applicant: FORD GLOBAL TECHNOLOGIES, LLCInventors: Karin Lovett, Jason C. Marcath, Thanh Duc Pham, Beth Ann Dalrymple, Jesus Cardoso, David Hayes, Hsiao-An Hsieh, Darko Acevski
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Publication number: 20130088347Abstract: A computer implemented method includes detecting a vehicle state for which a user is to be notified. The method also includes sending a notification for a user regarding the vehicle state. The method further includes receiving a response that a do not disturb mode is enabled for the user. The method additionally includes queuing the notification for later delivery. The method also includes re-sending the notification for the user at a later point in time than when an original notification was sent.Type: ApplicationFiled: October 5, 2011Publication date: April 11, 2013Applicant: FORD GLOBAL TECHNOLOGIES, LLCInventors: David Hayes, Thanh Duc Pham, Jesus Cardoso, Jason C. Marcath, Darko Acevski, Karin Lovett, Hsiao-An Hsieh, Beth Ann Dalrymple
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Publication number: 20120303995Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: ApplicationFiled: August 13, 2012Publication date: November 29, 2012Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Patent number: 8294500Abstract: A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.Type: GrantFiled: November 18, 2009Date of Patent: October 23, 2012Assignee: Altera CorporationInventors: Vinh Van Ho, Tien Duc Pham, Tim Tri Hoang, Van Ton-That
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Publication number: 20120251116Abstract: Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.Type: ApplicationFiled: January 27, 2012Publication date: October 4, 2012Applicant: ALTERA CORPORATIONInventors: Peng Li, Sergey Shumarayev, Jon M. Long, Tien Duc Pham
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Patent number: 8245073Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.Type: GrantFiled: July 24, 2009Date of Patent: August 14, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Aaron Nygren, Ming-Ju Edward Lee, Shadi Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael Litt
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Patent number: 8228102Abstract: One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.Type: GrantFiled: March 3, 2010Date of Patent: July 24, 2012Assignee: Altera CorporationInventors: Tien Duc Pham, Sergey Shumarayev, Richard G. Cliff, Tim Tri Hoang, Weiqi Ding, Sriram Narayan, Thungoc M. Tran, Kumara Tharmalingam
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Publication number: 20110208989Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.Type: ApplicationFiled: July 30, 2010Publication date: August 25, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Ming-Ju Edward Lee, Shadi M. Barakat, Xiaoling Xu, Toan Duc Pham, Warren Fritz Kruger, Michael John Litt