Abstract: A method for substantially reducing conductive line cracking on an integrated circuit, comprising the steps of: obtaining a semiconductor structure with a first surface and with an insulating region adjacent to and rising above the first surface; forming a layer of a first conductive material above the first surface of the semiconductor structure and above the adjacent first insulating region; forming an opening through the layer of first conductive material down to the first insulating region; forming an insulation layer over the layer of first conductive material; forming a layer of a second conductive material above the insulation layer; polishing the layer of second conductive material; and forming a third conductive layer above the layer of second conductive material.

Abstract: Methods and test platforms for developing an application-specific integrated circuit incorporating, on the same chip, a signal processor core, RAM memory and ROM memory intended to receive a management program and processing program, and input-output management peripherals specific to the application. The signal processor, RAM memory and ROM memory correspond respectively to existing separate IC components. The processing program is developed and tested on a test platform including at least these separate IC components together with a core-emulation integrated circuit, which includes the signal processor core in a minimal configuration. An interface program and diagnostic interface logic allows the platform to be controlled from a microcomputer, which can thereby implement automatic chaining of tests.