Abstract: A liquid crystal display according to an embodiment of the present invention includes: a first substrate; a pixel electrode formed on the first substrate; a first insulating layer formed on at least part of the pixel electrode; a sustain electrode line formed on the first insulating layer and over at least a portion of the pixel electrode so as to form a capacitance; a second insulating layer formed on the sustain electrode line; and a data line formed on the second insulating layer, the data line and sustain electrode line positioned so that the sustain electrode line is positioned between the data line and the pixel electrode.

Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A memory system includes an address remapping circuit and a first set of memory devices. The address remapping circuit includes a plurality of input terminals for receiving a plurality of chip selection signals and a plurality of chip identification signals. The address remapping circuit receives input signals corresponding to a portion of the plurality of chip selection signals and the plurality of chip identification signals through corresponding input terminals of the plurality of input terminals and generates a plurality of internal chip selection signals based on the input signals and a remapping control signal. Each of the first set of memory devices is configured to be selected in response to a corresponding internal chip selection signal of the plurality of internal chip selection signals.

Abstract: A method for manufacturing a touch sensor panel with a reduced number of masks includes forming a first resist layer with both full and partial thickness patterns, the latter being at a region corresponding to a plurality of first sensor electrodes; etching a first transparent conductive layer and a first other conductive layer using the first resist layer patterns having both full and partial thicknesses; forming a second resist layer with both full and partial thickness patterns, the latter being at a region corresponding to a plurality of second sensor electrodes; and etching while using the second resist layer patterns.

Abstract: A display panel includes: a pixel electrode including first, second, and third sub-pixel electrodes separated from each other; a first TFT connected to the first sub-pixel electrode; second and fourth TFTs connected to the second sub-pixel electrode; a third TFT connected to the third sub-pixel electrode; a first gate line connected to the first to third TFTs; a second gate line connected to the fourth TFT; a data line electrically insulated from and intersecting the first and second gate lines and connected to the first to third TFTs; and a storage electrode connected to the fourth TFT and overlapping the first sub-pixel electrode.

Abstract: A display device includes a display panel and a data driver. The display panel includes at least one gate line, at least two data lines, a display area including a pixel connected to the at least one gate line and the at least two data lines, and a peripheral area outside the display area, the peripheral area including a pair of fan-out wiring structures. The data driver is configured to apply data voltage to the at least two data lines. Each of the pair of fan-out wiring structures includes a bent structure, the bent structure of one of the pair of fan-out wiring structures includes the same material as the at least one gate line, and the bent structure of the remaining one of the pair of fan-out wiring structures includes the same material as the at least two data lines.

Abstract: A method of forming a metal pattern is disclosed. According to the method, a gate electrode and a pixel electrode are formed on a substrate. A metal layer is formed covering the gate electrode and the pixel electrode. A photo pattern is formed wherein a thickness of an area of the photo pattern that overlaps the gate electrode is smaller than a thickness of other areas of the photo pattern. The photo pattern is soft-baked. The photo pattern is exposed to light. The photo pattern is developed to expose a portion of the metal layer that overlaps the gate electrode. The exposed portion of the metal layer is removed to form a source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart from each other with respect to the gate electrode.

Abstract: A sensor substrate includes a blocking pattern disposed on a base substrate, a first electrode disposed on the base substrate and overlapping the blocking pattern, the first electrode including a plurality of first unit parts arranged in a first direction, each of the first unit parts including a plurality of lines connected to each other in a mesh-type arrangement, a color filter layer disposed on the base substrate, a plurality of contact holes defined in the color filter layer and exposing the first unit parts, and a bridge line between and connected to first unit parts adjacent to each other in the first direction, through the contact holes.

Abstract: A display panel includes: a pixel electrode comprising first, second, and third sub-pixel electrodes that are separated from each other; a first thin film transistor connected to the first sub-pixel electrode; second and fourth thin film transistors connected to the second sub-pixel electrode; third and fifth thin film transistors connected to the third sub-pixel electrode; a first gate line connected to the first to fourth thin film transistors; a second gate line connected to the fifth thin film transistor; a data line insulated from and intersecting the first and second gate lines and connected to the first to third thin film transistors; a first storage electrode line disposed adjacent to the first gate line; and a second storage electrode line disposed adjacent to the second gate line.

Abstract: An array substrate for a display device includes a first base substrate; a thin film transistor disposed on the first base substrate that includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode; a first passivation layer that covers the thin film transistor and that includes an inorganic insulating material; a second passivation layer disposed on the first passivation layer that includes an exposure hole that exposes the first passivation layer on the drain electrode; a common electrode disposed on the second passivation layer; a third passivation layer that covers the common electrode and that includes a contact hole inside the exposure hole to expose the drain electrode; a cavity between the first passivation layer and the third passivation layer on the drain electrode; and a pixel electrode disposed on the third passivation layer and connected with the drain electrode.

Abstract: A display apparatus including a first substrate, a second substrate, a pixel, and a unit color filter. The first and second substrates are opposite to each other. The pixel is disposed between the first and second substrates. The color filter is disposed between the first substrate and the pixel or between the second substrate and the pixel. The color filter includes a red color filter, a green color filter, a blue color filter, and a yellow color filter. The yellow color filter includes a sub-red color filter and a sub-green color filter.

Abstract: A thin film transistor display panel capable of minimizing a bezel and a manufacturing method thereof are provided. The thin film transistor display panel includes: a substrate; a plurality of gate lines and data lines that cross each other on the substrate; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a plurality of gate voltage supply lines arranged in a parallel direction with the data lines and connected to the plurality of gate lines, respectively, in which one pixel area is defined by two adjacent gate lines and two adjacent data lines, two pixel electrodes are formed in one pixel area, and the gate voltage supply lines pass between the two pixel electrodes formed in the same pixel area.

Abstract: A sensor substrate includes a blocking pattern disposed on a base substrate, a first electrode disposed on the base substrate and overlapping the blocking pattern, the first electrode including a plurality of first unit parts arranged in a first direction, each of the first unit parts including a plurality of lines connected to each other in a mesh-type arrangement, a color filter layer disposed on the base substrate, a plurality of contact holes defined in the color filter layer and exposing the first unit parts, and a bridge line between and connected to first unit parts adjacent to each other in the first direction, through the contact holes.

Abstract: A display device includes a first signal electrode configured to transfer a signal, a first insulating layer positioned on the first signal electrode, a first electrode positioned on the first insulating layer, a second insulating layer positioned on the first electrode, and a second electrode positioned on the second insulating layer, where a first contact hole exposing the first signal electrode is defined in the first insulating layer and the second insulating layer, the second electrode is connected with the first signal electrode through the first contact hole, and an opening including an edge side surrounding the first contact hole in a plan view is defined in the first electrode.

Abstract: A liquid crystal display includes a first substrate, gate lines and data lines disposed on a display area of the first substrate, a common voltage line disposed on a peripheral area of the first substrate, a common voltage transmission unit extending from the common voltage line, an organic layer disposed on the common voltage transmission unit and the common voltage line, a connecting member disposed on the organic layer disposed on the peripheral area, a first insulating layer disposed on the pixel electrode and the connecting member, a common electrode disposed on the first insulating layer, and a short point connecting the connecting member and the common electrode to each other. The common electrode and the first insulating layer include a plurality of cutouts in the peripheral region and display region of the first substrate which have substantially a same plane shape as each other.

Abstract: A three dimensional image display device includes a liquid crystal display panel assembly which includes a first pixel and a second pixel disposed adjacent to each other in a vertical direction. The first pixel comprises a first subpixel and a second subpixel disposed adjacent to each other in the vertical direction, and the second pixel includes a third subpixel and a fourth subpixel which are disposed adjacent to each other in the vertical direction. The first subpixel and the third subpixel, or the second subpixel and the fourth subpixel display black in a three dimensional (3D) display mode and display a normal image in a two dimensional (2D) display mode.

Abstract: A sensor substrate includes a blocking pattern disposed on a base substrate, a first electrode disposed on the base substrate and overlapping the blocking pattern, the first electrode including a plurality of first unit parts arranged in a first direction, each of the first unit parts including a plurality of lines connected to each other in a mesh-type arrangement, a color filter layer disposed on the base substrate, a plurality of contact holes defined in the color filter layer and exposing the first unit parts, and a bridge line between and connected to first unit parts adjacent to each other in the first direction, through the contact holes.

Abstract: An array substrate includes a thin film transistor which includes a gate electrode electrically connected to a gate line, a source electrode electrically connected to a data line, a drain electrode and an active layer, a first electrode electrically connected to the drain electrode and disposed at a pixel area, and a second electrode covering an upper and a side surface of the source electrode. The second electrode is spaced apart from the first electrode.

Abstract: Exemplary embodiments of the present disclosure provide a thin film transistor array panel including a first insulating substrate; a gate line and a data line disposed on the first insulating substrate, intersecting with each other, and being insulated from each other; a first passivation layer disposed on the gate line and the data line and comprising a plurality of first openings; a first electrode disposed on the first passivation layer; and a second electrode disposed in the first opening, thereby simplifying a manufacturing process of the thin film transistor array panel.

Abstract: A method for manufacturing a touch sensor panel with a reduced number of masks includes forming a first resist layer with both full and partial thickness patterns, the latter being at a region corresponding to a plurality of first sensor electrodes; etching a first transparent conductive layer and a first other conductive layer using the first resist layer patterns having both full and partial thicknesses; forming a second resist layer with both full and partial thickness patterns, the latter being at a region corresponding to a plurality of second sensor electrodes; and etching while using the second resist layer patterns.