Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. A charge pump apparatus and a memory integrated circuit are also described.

Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. A charge pump apparatus and a memory integrated circuit are also described.

Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.

Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.

Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.

Abstract: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.

Abstract: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

Abstract: A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.

Abstract: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

Abstract: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

Abstract: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

Abstract: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

Abstract: Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

Abstract: A method and apparatus for providing a preselected voltage to test or repair a semiconductor device. The apparatus includes a one-stage pump and a transfer device. The one-stage pump is adapted to access a first voltage and provide a second voltage using the first voltage. The transfer device is capable of providing the first voltage to a node using the second voltage.

Abstract: An output buffer circuit that compensates for ambient temperature changes facilitates more consistent current drive capacity across a range of ambient temperatures. The number of output buffer stages utilized to generate the data output signal is varied in response to changes in ambient temperature.

Abstract: An apparatus and method for compensating for a decreasing internal voltage that is generated from a higher external voltage. In response to the internal voltage decreasing in excess of a voltage margin, the amount by which the higher external voltage is reduced in generating the internal voltage is adjusted to raise the internal voltage.

Abstract: A symmetrical divide-by-2 circuit has a master latch made up of two inverters. The circuit has an inverter on each output. The capacitance of these inverters forms a dynamic slave latch that is connected to the master latch through a transmission gate on each master latch output. The data is transferred from the master latch to the dynamic slave latch every clock cycle by an enable clock and an inverse of the enable clock. Capacitance leakage is reduced by the transmission gates until the next clock cycle. The circuit is clocked by a one-shot clock that is self-aligning to the latest transition of either the enable clock or inverse enable clock.

Abstract: A transition of an external enable signal generates a reset pulse to a counter to set the counter into a known state. The counter, clocked by the external clock signal, generates a clock signal that is decoded by a fuse decoder circuit. The fuse decoder circuit outputs a selection signal to a trim circuit. The trim circuit produces a voltage selection signal, such as a resistance value, that is indicated by the selection signal for use by an internal reference voltage generation circuit. The output of the internal reference voltage generation circuit is compared to the external reference voltage. The counter circuit continues counting until the internal reference voltage is equal to or greater than the external reference voltage. The counter is disabled and the final count that produced the proper internal reference voltage is stored in non-volatile memory cells for future use.

Abstract: A symmetrical divide-by-2 circuit has a master latch made up of two inverters. The circuit has an inverter on each output. The capacitance of these inverters forms a dynamic slave latch that is connected to the master latch through a transmission gate on each master latch output. The data is transferred from the master latch to the dynamic slave latch every clock cycle by an enable clock and an inverse of the enable clock. Capacitance leakage is reduced by the transmission gates until the next clock cycle. The circuit is clocked by a one-shot clock that is self-aligning to the latest transition of either the enable clock or inverse enable clock.