Patents by Inventor Dung Nguyen

Dung Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060184768
    Abstract: Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few as one instruction per group to a maximum number of instructions read from the IBUF per cycle. The reformatted dispatch groupings can be terminated after a single cycle, or they can remain reformatted for as many cycles as desired, depending upon need.
    Type: Application
    Filed: February 11, 2005
    Publication date: August 17, 2006
    Applicant: International Business Machines Corporation
    Inventors: James Bishop, Hung Le, Jafar Nahidi, Dung Nguyen, Brian Thompto
  • Publication number: 20060184776
    Abstract: A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value in the LFSR, a mark bit, indicating the instruction is a marked instruction, is sent with the instruction to an execution unit. Responsive to an indication from the performance monitor, the value in the LFSR is incremented prior to selecting a next instruction to mark. If the value equals a predetermined prime number of increments, the value is reset to all ones to avoid any harmonics with the code stream being executed. Upon receiving the marked instruction, the execution unit combines the marked bit with a selected event and reports the marked event to the performance monitor.
    Type: Application
    Filed: February 11, 2005
    Publication date: August 17, 2006
    Applicant: International Business Machines Corporation
    Inventors: James Bishop, Michael Floyd, Alexander Mericas, Robert Mirabella, Dung Nguyen, Philip Vitale
  • Publication number: 20060179257
    Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Inventors: Sam Chu, Maureen Delaney, Saiful Islam, Dung Nguyen, Jafar Nahidi
  • Publication number: 20060179282
    Abstract: A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: Hung Le, Dung Nguyen, Raymond Yeung
  • Publication number: 20060179346
    Abstract: A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.
    Type: Application
    Filed: February 10, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: James Bishop, Hung Le, Michael Mack, Jafar Nahidi, Dung Nguyen, Jose Paredes, Scott Swaney, Brian Thompto
  • Publication number: 20060179286
    Abstract: A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: Juergen Haess, Michael Kroener, Dung Nguyen, Eric Schwarz, Son Dao-Trong, Raymond Yeung
  • Publication number: 20060179100
    Abstract: A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: Juergen Haess, Michael Kroener, Dung Nguyen, Lawrence Powell, Eric Schwarz, Son Dao-Trong, Raymond Yeung
  • Publication number: 20060179207
    Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
    Type: Application
    Filed: February 10, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: Susan Eisen, Hung Le, Michael Mack, Dung Nguyen, Jose Paredes, Scott Swaney
  • Publication number: 20060171208
    Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
    Type: Application
    Filed: January 27, 2005
    Publication date: August 3, 2006
    Inventors: Sam Chu, Maureen Delaney, Saiful Islam, Jafar Nahidi, Dung Nguyen
  • Publication number: 20060168393
    Abstract: An apparatus and method for dependency tracking and register file bypass controls using a scannable register file are provided. With the apparatus and method, a scannable register file array is provided and used to track the stage of any instruction in the execution unit. Every entry in the target vector is updated every cycle to stay synchronized with the instructions in the execution unit. To keep the register file array synchronized with the instructions in the execution unit, a right shift of all the data in each entry of the register file array occurs every cycle. The scan port of the register file array cells is used as the shift function.
    Type: Application
    Filed: January 27, 2005
    Publication date: July 27, 2006
    Inventors: Bjorn Christensen, Peter Klim, Dung Nguyen, Raymond Yeung
  • Publication number: 20060149935
    Abstract: The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled.
    Type: Application
    Filed: December 17, 2004
    Publication date: July 6, 2006
    Applicant: International Business Machines Corporation
    Inventors: Richard Eickemeyer, Hung Le, Dung Nguyen, Benjamin Stolt, Brian Thompto
  • Publication number: 20060149933
    Abstract: A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pending instructions which include at least one branch instruction during the stall condition, and determining the validity of data utilized by the speculative execution. In particular, the method can detect a load instruction miss which results in the stall condition. Dispatch logic determines the validity of the data by marking one or more registers of an instruction dispatch unit to indicate which results of the pending instructions are invalid.
    Type: Application
    Filed: December 17, 2004
    Publication date: July 6, 2006
    Inventors: Richard Eickemeyer, Hung Le, Dung Nguyen, Benjamin Stolt, Brian Thompto
  • Publication number: 20060149934
    Abstract: The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch.
    Type: Application
    Filed: December 17, 2004
    Publication date: July 6, 2006
    Inventors: Richard Eickemever, Hung Le, Dung Nguyen, Benjamin Stolt, Brian Thompto
  • Publication number: 20060136435
    Abstract: A system and computer-based method is provided for context-sensitive decomposition of a markup based document into a relational database, based on schemas with reusable item declarations. User creates a mapping document from a schema of a markup based document with at least one reusable item declaration defining an item being mapped to different tables/columns pairs, depending on the item's ancestry. Mapping document is then annotated with the item ancestry mapping annotation having a location path of the item. Each item is decomposed into a corresponding table column. Preferably, the mapping document is an annotated XML Schema.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Applicant: International Business Machines Corporation
    Inventors: Dung Nguyen, Mayank Pradhan
  • Publication number: 20060136363
    Abstract: A system and computer-based method is provided for decomposing and storing a markup based document into a relational database. For a schema of a markup based document a user identifies multiple items mapping into a same database table-column pair, creates a logical table and associates the logical table to each item and a corresponding database table. Next, a user creates a mapping document of the markup based document with mapping annotations defining mapping of the items into columns of the logical tables. Decomposition of each item into a corresponding logical table column is accomplished by collecting the item content from the markup based document and storing it in the corresponding row column.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Applicant: International Business Machines Corporation
    Inventors: Dung Nguyen, Mayank Pradhan
  • Publication number: 20060136483
    Abstract: A system and computer-based method is provided for decomposing and storing content of a markup based document into a relational database. For a schema of a markup based document a user identifies multiple items mapping into a same database table-column pair and associates a rowset to each such item and a corresponding database table. Next, the user creates a mapping document based on the schema of the markup based document with rowset-specific mapping annotations defining mapping of the items into columns of the rowsets. Decomposition of each item into a corresponding rowset column is accomplished by collecting the item content from the markup based document and storing it in the corresponding rowset column, for later storage in a database table.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 22, 2006
    Applicant: International Business Machines Corporation
    Inventors: Dung Nguyen, Mayank Pradhan
  • Publication number: 20060101241
    Abstract: A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads.
    Type: Application
    Filed: October 14, 2004
    Publication date: May 11, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Curran, Brian Konigsburg, Hung Le, David Luick, Dung Nguyen
  • Publication number: 20050228972
    Abstract: A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive number of outstanding instructions. Each entry may be configured to store an instruction address and an identification of a first of the consecutive number of outstanding instructions. By being able to track a consecutive number of outstanding instructions, such as the length of a cache line, in each entry in the completion table by only storing the instruction address and identification of the first of the consecutive number of outstanding instruction in that entry, the completion table may be able to track a larger number of outstanding instruction without increasing its size.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 13, 2005
    Applicant: International Business Machines Corporation
    Inventors: Susan Eisen, Hung Le, David Luick, Dung Nguyen
  • Patent number: 6921555
    Abstract: An apparatus and method for sequential and isolated processing of a workpiece comprises a two compartment chamber and a mechanism to transfer the workpiece from a first compartment to a second compartment by rotating the workpiece on a workpiece mover through an internal pathway. The transfer mechanism comprises two doors coupled to the workpiece mover to seal the internal pathway between the first and second compartments so that the two compartments are isolated and the workpiece can be processed sequentially and in isolation. The apparatus further comprises components to enable the processing of a workpiece. The preferred method of processing a workpiece is to deposit or adsorb a thin layer in the first compartment and then transfer by rotating the workpiece on the workpiece mover to the second compartment for further processing.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: July 26, 2005
    Assignee: Tegal Corporation
    Inventors: Tue Nguyen, Tai Dung Nguyen, Craig Alan Bercaw
  • Patent number: 6919101
    Abstract: A method for improving the adhesion of an impermeable film on a porous low-k dielectric film in an interconnect structure is disclosed. The method provides an in-situ annealing step before the deposition of the impermeable film to release the volatile trapped molecules such as water, alcohol, HCl, and HF vapor, inside the pores of the porous low-k dielectric film. The method also provides an in-situ deposition step of the impermeable film right after the deposition of the porous low dielectric film without exposure to an atmosphere containing trappable molecules. The method further provides an in-situ deposition step of the impermeable film right after the removal a portion of the porous low-k dielectric film without exposure to an atmosphere containing trappable molecules. By the removal of all trapped molecules inside the porous low-k dielectric film, the adhesion between the deposited impermeable film and the low-k dielectric film is improved.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: July 19, 2005
    Assignee: Tegal Corporation
    Inventors: Zhihong Zhang, Tai Dung Nguyen, Tue Nguyen