Patents by Inventor Dung Q. Nguyen

Dung Q. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ECC SCRUBBING METHOD IN A MULTI-SLICE MICROPROCESSOR
    Publication number: 20180095820
    Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data to an execution unit, where the first data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.
    Type: Application
    Filed: November 7, 2017
    Publication date: April 5, 2018
    Inventors: Brian D. Barrick, James W. Bishop, Maarten J. Boersma, Marcy E. Byers, Sundeep Chadha, Jentje Leenstra, Dung Q. Nguyen, David R. Terry
  • REDUCING POWER CONSUMPTION IN A MULTI-SLICE COMPUTER PROCESSOR
    Publication number: 20180088653
    Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 29, 2018
    Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
  • Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
    Patent number: 9928073
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • In-pipe error scrubbing within a processor core
    Patent number: 9928128
    Abstract: A supervisory hardware device in a processor core detects a flush instruction that, when executed, flushes content of one or more general purpose registers (GPRs) within the processor core. The content of the one or more GPRs is moved to a history buffer (HB) and an instruction sequencing queue (ISQ) within the processor core, where the content includes data, an instruction tag (iTag) that identifies an instruction that generated the data, and error correction code (ECC) bits for the data. In response to receiving a restore instruction, the supervisory hardware device error checks the data in the ISQ using the ECC bits stored in the ISQ. In response to detecting an error in the data in the ISQ, the supervisory hardware device sends the data and the ECC bits from the ISQ to an ECC scrubber to generate corrected data, which is restored into the one or more GPRs.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, James W. Bishop, Marcy E. Byers, Sundeep Chadha, Niels Fricke, Dung Q. Nguyen, David R. Terry
  • Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor
    Patent number: 9921833
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices coupled via a results bus includes: retrieving, from the results bus into an entry of a register file of an execution slice, speculative result data of a load instruction generated by a load/store slice; and determining, from the load/store slice after expiration of a predetermined period of time, whether the result data is valid.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • REDUCING POWER CONSUMPTION IN A MULTI-SLICE COMPUTER PROCESSOR
    Publication number: 20180074565
    Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
    Type: Application
    Filed: November 3, 2017
    Publication date: March 15, 2018
    Inventors: STEVEN J. BATTLE, OWEN CHIANG, SAM G. CHU, SAIFUL ISLAM, DUNG Q. NGUYEN, DAVID R. TERRY, EULA A. TOLENTINO
  • INDEPENDENT MAPPING OF THREADS
    Publication number: 20180067746
    Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 8, 2018
    Inventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
  • Age based fast instruction issue
    Patent number: 9880850
    Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
  • Independent mapping of threads
    Patent number: 9870229
    Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
  • Age based fast instruction issue
    Patent number: 9870231
    Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A 1-hot signal is generated that identifies an oldest ready instruction in the first age array and a 1-hot signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
  • Reducing power consumption in a multi-slice computer processor
    Patent number: 9870045
    Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • Reducing power consumption in a multi-slice computer processor
    Patent number: 9870039
    Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING PRIORITIZED DEPENDENCY CHAIN RESOLUTION
    Publication number: 20180004527
    Abstract: Operation of a computer processor that includes: receiving a first instruction indicating a first target register; receiving, from an instruction fetch unit of the computer processor, a first instruction and a branch instruction; responsive to determining that the branch instruction is dependent upon a result of the first instruction, updating a priority value corresponding to the first instruction; and issuing, in dependence upon the priority value for the first instruction having a higher priority than a priority value for another instruction, the first instruction to an execution unit of the computer processor.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: KHANDKER N. ADEEB, JOSHUA W. BOWMAN, BRANDON R. GODDARD, DUNG Q. NGUYEN, TU-AN T. NGUYEN, EULA A. TOLENTINO, BRIAN D. VICTOR, BRENDAN M. WONG
  • Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor
    Patent number: 9858078
    Abstract: An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry, Eula F. Tolentino
  • Split-level history buffer in a computer processing unit
    Patent number: 9851979
    Abstract: A split level history buffer in a central processing unit is provided. A first instruction and a second instruction are fetched, tagged, and the first instruction is stored an entry of a register file. The first instruction is evicted from the entry and the second instruction is stored in the entry. If the first instruction is evicted, then the first instruction is stored in a first portion of a history buffer. If a result for the first instruction is generated, then the first instruction is moved to a second portion of the history buffer and the result is stored with the first instruction in the second portion of the history buffer. If it is determined that a third instruction evicts the second instruction from the entry, then the second instruction is stored in the first portion of the history buffer.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • TECHNIQUES FOR IMPLEMENTING STORE INSTRUCTIONS IN A MULTI-SLICE PROCESSOR ARCHITECTURE
    Publication number: 20170364356
    Abstract: A technique for operating a processor includes receiving, at an issue queue, a store instruction that has an associated address generation (AGN) operation and an associated data operation. The AGN operation is issued to AGN logic associated with a pipeline slice in response to all source operands for the AGN operation being ready. The AGN logic is configured to generate an address for the store instruction. Confirmation, for the AGN operation is received. The confirmation includes an indication of the pipeline slice that performed the AGN operation. In response to receiving the confirmation and a source operand for the data operation being ready, the issue queue issues the data operation to data logic associated with the pipeline slice indicated by the confirmation. The data logic is configured to format data for the store instruction.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 21, 2017
    Inventors: SALMA AYUB, MAARTEN J. BOERSMA, SUNDEEP CHADHA, DAVID A. HRUSECKY, JENNIFER L. MOLNAR, DUNG Q. NGUYEN
  • OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DEPENDENCY ACCUMULATION INSTRUCTION SEQUENCING
    Publication number: 20170364358
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 21, 2017
    Inventors: KHANDKER N. ADEEB, JOSHUA W. BOWMAN, JEFFREY C. BROWNSCHEIDLE, BRANDON R. GODDARD, DUNG Q. NGUYEN, TU-AN T. NGUYEN, BRIAN D. VICTOR, BRENDAN M. WONG
  • ECC scrubbing in a multi-slice microprocessor
    Patent number: 9846614
    Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data and error correcting code data to an execution unit, where the first data and error correcting code data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: December 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Barrick, James W. Bishop, Maarten J. Boersma, Marcy E. Byers, Sundeep Chadha, Jentje Leenstra, Dung Q. Nguyen, David R. Terry
  • TRANSMITTING DATA BETWEEN EXECUTION SLICES OF A MULTI-SLICE PROCESSOR
    Publication number: 20170357513
    Abstract: Methods and apparatus for transmitting data between execution slices of a multi-slice processor including receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; calculating a cycle countdown using the latency and the source identifier; determining that the cycle countdown has expired; and in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.
    Type: Application
    Filed: June 9, 2016
    Publication date: December 14, 2017
    Inventors: SALMA AYUB, JOSHUA W. BOWMAN, JEFFREY C. BROWNSCHEIDLE, SUNDEEP CHADHA, DHIVYA JEGANATHAN, DUNG Q. NGUYEN, SALIM A. SHAH, BRIAN W. THOMPTO
  • OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING ADAPTIVE FAILURE STATE CAPTURE
    Publication number: 20170351583
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the load/store slices are coupled to the execution slices via a results bus. Operation of such a multi-slice processor includes: capturing first state information corresponding to a first set of control signals; monitoring state information of a plurality of logical components of the multi-slice processor; selecting, in dependence upon one or more selection criteria and upon the monitored state information, a second set of control signals; and capturing second state information corresponding to the second set of control signals, wherein the first set of control signals is different than the second set of control signals.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 7, 2017
    Inventors: KHANDKER N. ADEEB, STEVEN J. BATTLE, BRANDON R. GODDARD, DUNG Q. NGUYEN, TU-AN T. NGUYEN, NICHOLAS R. ORZOL, BRIAN D. VICTOR, BRENDAN M. WONG