Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Abstract: A soft input is obtained from a sense word corresponding to encoded host data read from the memory device and decoded using a parity-check matrix. A match array is maintained. Each iteration of an error correcting code operation a number of unsatisfied check nodes of a respective bit of the sense word is calculated for each bit of the sense word. A bit flip threshold from a threshold data structure is obtained based on a current iteration of the error correcting code operation, a soft bit associated with the respective bit, and a match bit associated with the respective bit. The respective bit is flipped based on the number of unsatisfied check nodes satisfying the bit flip threshold.

Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

Abstract: Described are systems and methods for dynamically configurable data modulation in memory systems. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations, comprising: receiving a unit of data to be stored on the memory device; identifying a set of parameter values characterizing a target location of the unit of data on the memory device; determining a modulation code corresponding to the set of parameter values; modulating the unit of data by a modulation operation identified by the modulation code; and storing, on the memory device, the modulated unit of data.

Abstract: Described are systems and methods for adaptable data modulation. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations, comprising: receiving a unit of data to be written to the memory device; splitting the unit of data into a plurality of segments; modulating each segment of the unit of data by a modulation operation using a modulation mask derived from a corresponding seed value; and generating a modulated unit of data comprising a plurality of modulated segments and a plurality of corresponding seed identifiers, wherein each seed identifier identifies a seed value that has been used for modulating a respective segment of the unit of data.

Abstract: Described are systems and methods for selecting a modulation code permutation for data modulation in a memory system. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations including: receiving data to be written to the memory device; selecting, from a set of modulation code permutations for modifying data to be written to the memory device, a modulation code permutation; determining that a cost metric value corresponding to storing data modified by the modulation code permutation on the memory device satisfies a target condition; generating, using the modulation code permutation, modulated data from the data to be written; and storing, on the memory device, the modulated data.

Abstract: Host data to be programmed to a plurality of memory cells associated with a wordline of a memory device is received from a host system. The host data into a plurality of partitions is divided. Each of the plurality of partitions is divided into a respective plurality of sub-partitions. One or more modulation mappings to be applied to the plurality of sub-partitions are determined based on the host data of the plurality of partitions. Host data of each sub-partition of the plurality of sub-partitions is modified based on the one or more modulation mappings. The modified host data of each sub-partition is written to the plurality of memory cells associated with the wordline.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including storing a set of user data and multiple portions of error correction data. The operations can also include, responsive to an expiration of a first threshold amount of time after storing the set of user data, performing, using the third portion of the error correction data, a first error correction operation, on each of the set of user data, the first portion, and the second portion, and rewriting, on the memory device, the set of user data, the first portion, and the second portion. The operations can further include deleting the third portion.

Abstract: Input data is received for storage by a system. The input data is encoded using a low-density parity-check (LDPC) matrix to generate encoded data, wherein the LDPC matrix is selected from a plurality of LDPC matrices, each of the plurality of LDPC matrices having a common size and a unique degree distribution. The encoded data is then stored on a memory device of the system.

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether a memory device that stores the data referenced by the request satisfies a weak memory device criterion in view of a quality rating for the device. In response to a determination that the memory device satisfies the weak memory device criterion, an error correction operation to access the data is performed in accordance with the request.

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.

Abstract: Described are systems and methods for memory read threshold tracking based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a metric characterizing threshold voltage distributions of a subset of a set of the plurality of memory cells; determining a first voltage threshold adjustment value; receiving a second value of the metric; determining a second voltage threshold adjustment value; and applying the second voltage threshold adjustment value for reading the set of the plurality of memory cells.

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Abstract: Described are memory devices producing metadata characterizing the applied read voltage level with respect to voltage distributions. An example memory sub-system comprises: a memory device comprising a plurality of memory cells; and a controller coupled to the memory device, the controller to perform operations comprising: performing, using a read voltage level, a read strobe with respect to a subset of the plurality of memory cells; and receiving, from the memory device, one or more metadata values characterizing the read voltage level with respect to threshold voltage distributions of the subset of the plurality of memory cells, wherein the one or more metadata values reflect a conductive state of one or more bitlines connected to the subset of the plurality of memory cells.

Abstract: Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.

Abstract: In some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. The controller may apply a function to the first metric to obtain a second memory read configuration. The controller may obtain a second metric associated with the memory using the second memory read configuration. The controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. The controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. The controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.

Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metadata characterizing voltage distributions. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: receiving one or more metadata values characterizing threshold voltage distributions of a subset of the plurality of memory cells connected to one or more bitlines, wherein the one or more metadata values reflect a conductive state of the one or more bitlines; determining a read voltage adjustment value based on the one or more metadata values; and applying the read voltage adjustment value for reading the subset of the plurality of memory cells.