Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

Abstract: Systems and methods for selecting an optimal error recovery procedure for correcting a read error in a solid-state drive are provided. A machine learning model is trained to forecast which error recovery procedure of a plurality of error recovery procedures is most likely to achieve a predetermined goal given a state of a solid-state drive. The predetermined goal is based on at least one of a read latency and a failure rate of the solid-state drive. A current state of the solid-state drive is determined. An error recovery procedure is selected from among the plurality of error recovery procedures by inputting the current state of the solid-state drive into the trained machine learning model, thereby triggering the trained machine learning model to output the selected error recovery procedure. The selected error recovery procedure is executed to recover data from the solid-state drive.

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Abstract: A storage access request to access a solid state drive (SSD) is received. A storage access timer is set with a time duration, where the time duration is based on a desired performance of the SSD. A non-volatile memory command associated with the storage access request is sent to non-volatile memory. The storage access timer is started. A determination is made whether the non-volatile memory completed execution of the non-volatile memory command after the storage access timer indicates that the time duration elapsed. An indication that the storage access request is complete is sent to a host if the non-volatile memory completed execution of the non-volatile memory command. Alternatively, the storage access timer is reset with the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.

Abstract: Systems and methods for selecting an optimal error recovery procedure for correcting a read error in a solid-state drive are provided. A machine learning model is trained to forecast which error recovery procedure of a plurality of error recovery procedures is most likely to achieve a predetermined goal given a state of a solid-state drive. The predetermined goal is based on at least one of a read latency and a failure rate of the solid-state drive. A current state of the solid-state drive is determined. An error recovery procedure is selected from among the plurality of error recovery procedures by inputting the current state of the solid-state drive into the trained machine learning model, thereby triggering the trained machine learning model to output the selected error recovery procedure. The selected error recovery procedure is executed to recover data from the solid-state drive.

Abstract: Systems and methods are provided for decoding a codeword having a first codeword length using a decoding system. The systems and methods include receiving a vector corresponding to the codeword at the decoding system, wherein the decoding system comprises a first decoder and a second decoder, the first decoder is available to concurrently process codewords up to the first codeword length, and the second decoder is available to concurrently process codewords up to a second codeword length. The systems and methods further include determining that the received vector is to be decoded using the second decoder, partitioning the received vector of the first codeword length into a plurality of segments having a size no larger than the second codeword length, and decoding the plurality of segments using the second decoder.

Abstract: A storage access request to access a solid state drive (SSD) is received. A storage access timer is set with a time duration, where the time duration is based on a desired performance of the SSD. A non-volatile memory command associated with the storage access request is sent to non-volatile memory. The storage access timer is started. A determination is made whether the non-volatile memory completed execution of the non-volatile memory command after the storage access timer indicates that the time duration elapsed. An indication that the storage access request is complete is sent to a host if the non-volatile memory completed execution of the non-volatile memory command. Alternatively, the storage access timer is reset with the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.

Abstract: System and methods described herein includes a method for iterative decoding. The method includes instantiating an iterative decoding procedure to decode a codeword. At each iteration of the iterative decoding procedure, the method further includes retrieving information relating to a plurality of current decoding variables at a current iteration, determining a first current decoding variable to be skipped for the current iteration based on the information, and processing a second decoding variable without processing the first decoding variable to update related decoding variables from the plurality of current decoding variables.

Abstract: Systems and methods are provided for decoding a codeword of a low density parity check (LDPC) code. The systems and methods may include receiving a vector corresponding to the codeword encoded with a parity check matrix, and processing a first portion of the received vector with a first portion of the parity check matrix to obtain a decoding estimate of a first portion of the codeword. The systems and methods may further include processing the decoding estimate of the first portion of the codeword with a second portion of the parity check matrix to obtain an intermediate vector, and processing a second portion of the received vector with a third portion of the parity check matrix and the intermediate vector to obtain a decoding estimate of a second portion of the codeword.

Abstract: System and methods described herein includes a method for iterative decoding. The method includes instantiating an iterative decoding procedure to decode a codeword. At each iteration of the iterative decoding procedure, the method further includes retrieving information relating to a plurality of current decoding variables at a current iteration, determining a first current decoding variable to be skipped for the current iteration based on the information, and processing a second decoding variable without processing the first decoding variable to update related decoding variables from the plurality of current decoding variables.

Abstract: Systems and methods are provided for iterative data decoding. Decoding circuitry receives a first message from a variable node at a check node. Decoding circuitry generates a second message based at least in part on the first message. Decoding circuitry transmits the second message to the variable node. Decoding circuitry updates a hard decision value of the variable node based at least in part on the first message and the second message.

Abstract: A system including a first module, a second module and a third module. The first module is configured to generate a first parity check matrix. The second module is configured to append an appended matrix to the first parity check matrix to generate a resultant parity check matrix. The appended matrix includes additional elements. The third module is configured to receive user data and encode the user data based on the resultant parity check matrix.

Abstract: Systems and methods are provided for decoding a codeword having a first codeword length using a decoding system. The systems and methods include receiving a vector corresponding to the codeword at the decoding system, wherein the decoding system comprises a first decoder and a second decoder, the first decoder is available to concurrently process codewords up to the first codeword length, and the second decoder is available to concurrently process codewords up to a second codeword length. The systems and methods further include determining that the received vector is to be decoded using the second decoder, partitioning the received vector of the first codeword length into a plurality of segments having a size no larger than the second codeword length, and decoding the plurality of segments using the second decoder.

Abstract: A decoder including a compression module configured to select one or more nodes from a plurality of nodes associated with data being decoded by the decoder, where each node includes one or more bits, and to compress the one or more bits associated with the selected nodes. A memory is configured to store the compressed one or more bits associated with the selected nodes.

Abstract: Systems and methods are provided for decoding a codeword of a low density parity check (LDPC) code. The systems and methods may include receiving a vector corresponding to the codeword encoded with a parity check matrix, and processing a first portion of the received vector with a first portion of the parity check matrix to obtain a decoding estimate of a first portion of the codeword. The systems and methods may further include processing the decoding estimate of the first portion of the codeword with a second portion of the parity check matrix to obtain an intermediate vector, and processing a second portion of the received vector with a third portion of the parity check matrix and the intermediate vector to obtain a decoding estimate of a second portion of the codeword.

Abstract: Systems and methods are provided for decoding data. A decoder receives a variable node value and reliability data for a variable node, and check node values for check nodes associated with the variable node. Circuitry generates an updated variable node value, based on the received reliability data and the received check node values. The circuitry also generates, for at least one check node, an updated check node value based on the updated variable node value.

Abstract: Systems and methods are provided for decoding data. A decoder receives a plurality of variable node values for a plurality of variable nodes and processed reliability data for at least a subset of the plurality of variable nodes. Circuitry updates the variable node values based on the variable node values and the processed reliability data. The processed reliability data represents a version of the reliability data for at least the subset of the plurality of variable nodes.

Abstract: Systems and methods are provided for decoding data. A variable node value for a variable node is received at a first time, and reliability data for the variable node is received at a second time. The variable node is decoded using a first decoding scheme after the first time and before the second time, and the variable node is decoded using a second decoding scheme different from the first decoding scheme after the second time.

Abstract: Systems and methods are provided for decoding data. A decoder receives a plurality of variable node values for a plurality of variable nodes and processed reliability data for at least a subset of the plurality of variable nodes. Circuitry updates the variable node values based on the variable node values and the processed reliability data. The processed reliability data represents a version of the reliability data for at least the subset of the plurality of variable nodes.

Abstract: Systems and methods are provided for decoding data. A variable node value for a variable node is received at a first time, and reliability data for the variable node is received at a second time. The variable node is decoded using a first decoding scheme after the first time and before the second time, and the variable node is decoded using a second decoding scheme different from the first decoding scheme after the second time.