Patents by Inventor Dusan Petranovic
Dusan Petranovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8667446Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: March 29, 2010Date of Patent: March 4, 2014Assignee: Mentor Graphics CorporationInventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Publication number: 20110185323Abstract: Techniques for performing physical verification processes for stacked integrated circuit devices. An interface between a first two-dimensional integrated circuit device and a second two-dimensional integrated circuit device is identified. The design data for the identified layers in the first and second two-dimensional integrated circuit devices are then combined and physically verified as a single set of interface design data. The design data for the first two-dimensional integrated circuit device and the second two-dimensional integrated circuit device are then separately physically verified. Once the interface design data, the first two-dimensional integrated circuit device design data and the second two-dimensional integrated circuit device design data have been physically verified, the verified design can be recombined to form verified design data corresponding to a stacked integrated circuit device.Type: ApplicationFiled: August 23, 2010Publication date: July 28, 2011Inventors: WILLIAM MATTHEW HOGAN, DUSAN PETRANOVIC, ARA ASLYAN
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Patent number: 7900184Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.Type: GrantFiled: December 16, 2008Date of Patent: March 1, 2011Assignee: LSI CorporationInventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Publication number: 20100251191Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: ApplicationFiled: March 29, 2010Publication date: September 30, 2010Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Patent number: 7689962Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: GrantFiled: February 8, 2007Date of Patent: March 30, 2010Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Publication number: 20090100319Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.Type: ApplicationFiled: December 16, 2008Publication date: April 16, 2009Inventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Patent number: 7467359Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.Type: GrantFiled: November 3, 2005Date of Patent: December 16, 2008Assignee: LSI CorporationInventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Publication number: 20070226659Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.Type: ApplicationFiled: February 8, 2007Publication date: September 27, 2007Inventors: Roberto Suaya, Rafael Escovar, Shrinath Thelapurath, Salvador Ortiz, Dusan Petranovic
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Publication number: 20060067436Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.Type: ApplicationFiled: November 3, 2005Publication date: March 30, 2006Inventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Patent number: 7017126Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.Type: GrantFiled: November 26, 2002Date of Patent: March 21, 2006Assignee: LSI Logic CorporationInventors: Miodrag Potkoniak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Patent number: 6948114Abstract: A method for decoding an encoded signal. A first step generates a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics. A second step generates a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics. A third step replaces the selected subset of first precision state metrics with the second precision state metrics. A fourth step stores the first precision state metrics and the second precision state metrics.Type: GrantFiled: April 25, 2002Date of Patent: September 20, 2005Assignee: LSI Logic CorporationInventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Patent number: 6901571Abstract: A method for optimal placement of cells on a surface of an integrated circuit, comprising the steps of comparing a placement of cells to predetermined cost criteria and moving cells to alternate locations on the surface if necessary to satisfy the cost criteria. The cost criteria include a timing criterion based upon interconnect delay, where interconnect delay is modeled as a RC tree expressed as a function of pin-to-pin distance. The method accounts for driver to sink interconnect delay at the placement level, a novel aspect resulting from use of the RC tree model, which maximally utilizes available net information to produce an optimal timing estimate. Preferred versions utilize a RC tree interconnect delay model that is consistent with timing models used at design levels above placement, such as synthesis, and below placement, such as routing. Additionally, preferred versions can utilize either a constructive placement or iterative improvement placement method.Type: GrantFiled: January 21, 1998Date of Patent: May 31, 2005Assignee: LSI Logic CorporationInventors: Dusan Petranovic, Ranko Scepanovic, Ivan Pavisic
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Publication number: 20030226120Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.Type: ApplicationFiled: November 26, 2002Publication date: December 4, 2003Applicant: LSI LOGIC CORPORATIONInventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Publication number: 20030204809Abstract: A method for decoding an encoded signal. The method generally comprises the steps of (A) generating a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics, (B) generating a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics, (C) replacing the selected subset of first precision state metrics with the second precision state metrics, and (D) storing the first precision state metrics and the second precision state metrics.Type: ApplicationFiled: April 25, 2002Publication date: October 30, 2003Applicant: LSI LOGIC CORPORATIONInventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
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Patent number: 6546541Abstract: A method and apparatus are provided for generating constraints for an integrated circuit logic re-synthesis algorithm. The method and apparatus receive a netlist of interconnected logic elements, which includes a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element. The method and apparatus also receive a maximum allowable input ramp time specification for the logic elements and an output ramp time specification for the net driver logic elements. A maximum interconnect capacitance constraint is then generated for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.Type: GrantFiled: February 20, 2001Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventors: Dusan Petranovic, Ivan Pavisic, Aiguo Lu
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Patent number: 6532585Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.Type: GrantFiled: November 14, 2000Date of Patent: March 11, 2003Assignee: LSI Logic CorporationInventors: Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
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Patent number: 6499003Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.Type: GrantFiled: March 3, 1998Date of Patent: December 24, 2002Assignee: LSI Logic CorporationInventors: Edwin Jones, Dusan Petranovic, Ranko Scepanovic, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
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Publication number: 20020004714Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.Type: ApplicationFiled: March 3, 1998Publication date: January 10, 2002Inventors: EDWIN JONES, DUSAN PETRANOVIC, RANKO SCEPANOVIC, RICHARD SCHINELLA, NICHOLAS F. PASCH, MARIO GARZA, KEITH K. CHAO, JOHN V. JENSEN, NICHOLAS K. EIB
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Patent number: 6263299Abstract: An aerial image produced by a mask having transmissive portions is simulated by dividing the transmissive portions of the mask into primitive elements, obtaining a response for each of the primitive elements, and then simulating the aerial image by combining the responses over all of the primitive elements.Type: GrantFiled: January 19, 1999Date of Patent: July 17, 2001Assignee: LSI Logic CorporationInventors: Stanislav V. Aleshin, Evgenij Egorov, Genadij V. Belokopitov, Dusan Petranovic
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Patent number: 6174630Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.Type: GrantFiled: March 3, 1998Date of Patent: January 16, 2001Assignee: LSI Logic CorporationInventors: Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib