Patents by Inventor Dusan Petranovic

Dusan Petranovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6175953
    Abstract: The present invention is a method and apparatus for systematically applying proximity corrections to a mask pattern, wherein the pattern is divided into a grid of equally sized grid rectangles, an inner rectangle comprising a plurality of grid rectangles is formed, an outer rectangle comprising a second plurality of grid rectangles and the inner rectangle is formed and proximity correction is applied to the pattern contained within the inner rectangle as a function of the pattern contained within the outer rectangle.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: January 16, 2001
    Assignee: LSI Logic Corporation
    Inventors: Ranko Scepanovic, Dusan Petranovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
  • Patent number: 6171731
    Abstract: An aerial image produced by a mask having transmissive portions is simulated by dividing the transmissive portions of the mask into primitive elements and obtaining a spatial frequency function corresponding to each of the primitive elements. The spatial frequency functions corresponding to the primitive elements are combined to obtain a transformed mask transmission function, and the transformed mask transmission function is utilized to generate a simulation of the aerial image.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: January 9, 2001
    Assignee: LSI Logic Corporation
    Inventors: Marina G. Medvedeva, Ranko Scepanovic, Dusan Petranovic
  • Patent number: 6109201
    Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the cells. Designing of the IC's require meeting real-world constraints one of which is the performance of the IC, or the period of time required by the integrated circuit to produce the output signals from the time the input signals are available. Typically, the performance of an integrated circuit is determined by the slowest path of the signals, called the critical path. The critical path is usually only a small portion of the IC. The present invention discloses a method and apparatus for transforming the circuits comprising the critical path, thereby increasing the performance of the entire IC. The transformation is performed by segmenting, or blocking, the cells which make up the critical path. Then, each block is transformed, or replaced, with a resynthesized circuit to which both the digital 0 and digital 1 values are provided.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: August 29, 2000
    Assignee: LSI Logic Corporation
    Inventors: Dusan Petranovic, Ranko Scepanovic, Stanislav V. Aleshin, Mikhail Grinchuk, Sergei Gashov