Abstract: An electrical device comprising a reconfigurable integrated circuit that includes paired top electrodes and bottom electrodes separated from each other by an active layer.

Abstract: An electrical device comprising a reconfigurable integrated circuit that includes paired top electrodes and bottom electrodes separated from each other by an active layer.

Abstract: An electrical system comprising a circuit of reconfigurable electrical devices and a controller including a processor. The processor has a configuration examiner and a state modifier. The configuration examiner is configured to determine a configuration for the circuit of reconfigurable electrical devices based upon a connection input. The state modifier is configured to modify, based on the configuration, the circuit by changing a resistance state of the reconfigurable electrical devices. A controller for reconfigurable electrical devices and a method of controlling reconfigurable electrical devices of a circuit are also described.

Abstract: An electrical system comprising a circuit of reconfigurable electrical devices and a controller including a processor. The processor has a configuration examiner and a state modifier. The configuration examiner is configured to determine a configuration for the circuit of reconfigurable electrical devices based upon a connection input. The state modifier is configured to modify, based on the configuration, the circuit by changing a resistance state of the reconfigurable electrical devices. A controller for reconfigurable electrical devices and a method of controlling reconfigurable electrical devices of a circuit are also described.

Abstract: A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

Abstract: A network node (bridge, switch, router) and method for traffic interconnection in a communication network. The node includes an interconnection network or switch fabric having ingress and egress ports in communication with the input and output ports of the node. The interconnection network also includes an interconnector having a retiming module, a permutation module, and a re-alignment module. Data arriving at the node input ports is provided to the ingress queues of the interconnection network where it is queued, if necessary, and then processed through the interconnector so that it can be provided to an appropriate egress port. Data at the egress ports is then provided to output ports for transmission toward its intended destination.

Abstract: A manner of processing bit-interleaved data traffic in a communication network. In the increasingly-common scenario where data traffic is bit interleaved and scrambled using a PRBS (pseudo-random binary sequence) before it is transmitted from a sender to a receiver, the receiver is configured to receive the transmitted bit stream and decimate it, that is, remove the bits of the bit stream that are allocated for the receiver, prior to descrambling. To accomplish this, the receiver employs an LFSR (linear feedback shift register) similar or identical to the one used by the sender to scramble the data. The LFSR is initialized by employing helper bits inserted by the sender or an initialization unit, and may employ other techniques for phase adjustment or state skipping depending on the nature of the transmitted bit stream.

Abstract: A manner of processing data for transmission in a data communication network. A node having a main memory and an interleaver is provided. Received data is stored in the main memory and a bandwidth map is prepared. The data is then selectively read out and pre-processed according to the bandwidth map and stored in an interleaver memory. The data is later read out and post-processed before interleaving into a downstream data frame. The pre- and post-processing provide the data in a more efficient form for interleaving.

Abstract: A system and method for analyzing network power consumption is disclosed. The system and method for analyzing network power consumption includes the steps of specifying at least one service which will run on said network; defining a plurality of resources provisioned in the network, each having an associated power efficiency; associating a network path with the service; calculating a sum of the power efficiencies for the resources of the network path; and outputting the sum to a display device. The system and method for analyzing network power consumption is particularly useful for identifying power consumption efficiencies throughout a communication network.

Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

Abstract: A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer.

Abstract: A network node (bridge, switch, router) and method for traffic interconnection in a communication network. The node includes an interconnection network or switch fabric having ingress and egress ports in communication with the input and output ports of the node. The interconnection network also includes an interconnector having a retiming module, a permutation module, and a re-alignment module. Data arriving at the node input ports is provided to the ingress queues of the interconnection network where it is queued, if necessary, and then processed through the interconnector so that it can be provided to an appropriate egress port. Data at the egress ports is then provided to output ports for transmission toward its intended destination.

Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

Abstract: In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

Abstract: A manner of providing an energy-efficient two-stage PON using a multistage-PON repeater to forward data traffic and other communications between the first stage and the second stage. The multistage-PON repeater receives BI-PON transmission frames from and OLT and decimates them, forwarding data intended for end devices of the second stage. The multistage-PON repeater rate adapts the transmissions so that faster speeds may be associated with PON first stage communications and slower speeds are associated with PON second stage communications. Many though not all of the multistage-PON components are configured to operate at the slower clock speed, conserving energy. Upstream transmissions from the end devices of the second stage are buffered in the multistage-PON repeater and forwarded to the OLT according to an allocation schedule received from the OLT in a BI-PON frame.

Abstract: A manner of processing data for transmission in a data communication network. Node having a main memory and an interleaver is provided. Received data is stored in the main memory and a bandwidth map is prepared. The data is then selectively read out and pre-processing according to the bandwidth map and stored in an interleaver memory. The date is later read out and post-processed before interleaving into a downstream data frame. The pre- and post-processing provide the data in a more efficient form for interleaving.

Abstract: A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.

Abstract: A routing device such as either a 1:N demultiplexer or N:1 multiplexer can provide a power dissipation proportional to log2(N) by augmenting a conventional data demultiplexer/multiplexer with additional control circuitry. The control circuit ensures that control signals that trigger configuration of individual demultiplexer/multiplexer elements are propagated only along a data transmission path. Logic components of the control circuitry enable the multiplexers to be self-configuring and to prevent multiplexers from switching to elements with empty data buffers.

Abstract: A method and apparatus for controlling traffic in an optical network having a plurality of OLTs for communicating with a plurality of PONs. A traffic controller receives traffic information concerning current traffic volume and, preferably with reference to a rules database, calculates the number of OLTs required to support the current traffic volume. A separate determination may be made whether a network reconfiguration is permitted at this time. If a reconfiguration is permitted, the traffic controller configures a traffic control switch to route the PON traffic to an from only the calculated number of OLTs. The traffic control switch may be implemented using a voltage-controlled optical fiber coupling or electronically, routing the traffic as electrical signals to and from electro-optical converters associated with each PON. The OLTs to be used may be selected by the traffic controller.