Abstract: In a frame synchronous scrambled communications network, communications are protected from pathological bit patterns that may lead to loss of receiver lock by detecting a pathological bit pattern in an incoming traffic stream using a pathological pattern detector. When a pathological bit pattern, such as a transition-less bit pattern, is detected, a corrective bit pattern is generated and inserted or substituted into the incoming traffic stream before transmission to the receiver. The receiver can be configured to revert the modified traffic stream back to the original traffic stream.

Abstract: A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer.

Abstract: In a TDMA optical network, a clock data recovery module uses signal oversampling and preamble correlation together with enhanced performance modules to extract additional data from the upstream transmission signal. Information including duty cycle, ONT power estimation, signal noise and jitter can be extracted from the upstream signal using digital logic and used to tune network components and/or alleviate network conditions.

Abstract: In a dual rate gigabit passive optical network, an optical line termination (OLT) transmits a first rate (GPON) message frame interleaved with a second rate (NGPON) message frame. An unused ATM partition of the GPON message frame is provided with a header and payload portion of the NGPON message frame so that the message frame remains at a predetermined length required by the network.

Abstract: A processing device, configured to implement at least a portion of a scheduled medium-access protocol (SMAP) in a communication system, comprises a processor, a memory coupled to the processor, and one or more additional hardware modules. The functionality of the portion of the SMAP implemented in the processing device is partitioned between software, stored in the memory and executable by the processor, and hardware comprising the one or more additional hardware modules. In an illustrative embodiment, the processing device comprises a head-end device of a passive optical network, and the functionality comprises at least a scheduler and a grant generator, with the scheduler being implemented in the software and the grant generator being implemented in the hardware.

Abstract: A method and apparatus for clock and data recovery that is advantageous in burst-mode systems is disclosed. This clock and data recovery method allows a) fast locking to a rapidly changed phase of the transmission clock, and b) stable tracking of a slowly changing phase of the transmission clock. Such fast locking minimizes the “guard band” between consecutive transmission bursts, while stable tracking provides reliable data tracking, resulting in the efficient use of bandwidth. A plurality of clock signals, is generated, each having a different phase. The phase of an input signal data stream is determined and a desired clock signal in the plurality that corresponds to the phase of the input data stream is selected and used to sample the input signal data stream.

Abstract: A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.

Abstract: A communication device comprises a receiver and a data recovery module. The receiver may be an element of a serial transceiver embedded in or otherwise associated with an FPGA or other type of reconfigurable hardware. The receiver is operable with an unlocked sampling clock. The data recovery module is configured to detect transition edges in data signal samples generated by the receiver using the unlocked sampling clock, and to determine from the detected edges a sampling point for use in recovery of the associated data. The data recovery module is further configured to provide adjustment in the sampling point in the presence of transition edge variations, such as one or more exception conditions, that are attributable to the unlocked sampling clock.

Abstract: A processing device, configured to implement at least a portion of a scheduled medium-access protocol (SMAP) in a communication system, comprises a processor, a memory coupled to the processor, and one or more additional hardware modules. The functionality of the portion of the SMAP implemented in the processing device is partitioned between software, stored in the memory and executable by the processor, and hardware comprising the one or more additional hardware modules. In an illustrative embodiment, the processing device comprises a head-end device of a passive optical network, and the functionality comprises at least a scheduler and a grant generator, with the scheduler being implemented in the software and the grant generator being implemented in the hardware.

Abstract: Systems and techniques for multiple bit rate optical data transmission. A passive optical network includes an optical line termination unit (OLT) connected to one or more optical network units (ONUs) by optical elements. The OLT is capable of performing downstream transmission to the ONUs at each of a variety of different bit rates, and each ONU performs upstream transmission at one or more bit rates. The OLT can sense a bit rate of a received transmission and change its operation so as to receive and process the transmission exhibiting the sensed bit rate. Each of the ONUs receives and processes downstream transmissions at one or more bit rates, but each ONU is capable of maintaining a phase and frequency lock to downstream transmissions at all bit rates supported by the OLT. One or more of the ONUs may also receive and process downstream transmissions exhibiting different or changed bit rates.

Abstract: A method and apparatus for clock and data recovery that is advantageous in burst-mode systems is disclosed. This clock and data recovery method allows a) fast locking to a rapidly changed phase of the transmission clock, and b) stable tracking of a slowly changing phase of the transmission clock. Such fast locking minimizes the “guard band” between consecutive transmission bursts, while stable tracking provides reliable data tracking, resulting in the efficient use of bandwidth. A plurality of clock signals, is generated, each having a different phase. The phase of an input signal data stream is determined and a desired clock signal in the plurality that corresponds to the phase of the input data stream is selected and used to sample the input signal data stream.

Abstract: A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.