Patents by Inventor Dustin P. Wood
Dustin P. Wood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10522455Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.Type: GrantFiled: January 31, 2019Date of Patent: December 31, 2019Assignee: INTEL CORPORATIONInventors: Mathew J. Manusharow, Dustin P. Wood, Debendra Mallik
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Publication number: 20190164881Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 31, 2019Publication date: May 30, 2019Inventors: Mathew J. MANUSHAROW, Dustin P. WOOD, Debendra MALLIK
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Patent number: 10242942Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.Type: GrantFiled: April 25, 2014Date of Patent: March 26, 2019Assignee: INTEL CORPORATIONInventors: Mathew J. Manusharow, Dustin P. Wood, Debendra Mallik
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Publication number: 20170154842Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 25, 2014Publication date: June 1, 2017Inventors: Mathew J. MANUSHAROW, Dustin P. WOOD, Debendra MALLIK
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Patent number: 7755165Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.Type: GrantFiled: January 10, 2008Date of Patent: July 13, 2010Assignee: Intel CorporationInventors: Cengiz A. Palanduz, Dustin P. Wood
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Patent number: 7687905Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.Type: GrantFiled: February 28, 2008Date of Patent: March 30, 2010Assignee: Intel CorporationInventors: Brent S. Stone, Dustin P. Wood, Kaladhar Radhakrishnan
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Patent number: 7667320Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.Type: GrantFiled: January 30, 2008Date of Patent: February 23, 2010Assignee: Intel CorporationInventors: Dustin P. Wood, Kaladhar Radhakrishnan
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Patent number: 7656644Abstract: A method including depositing a suspension of a colloid having an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device having a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate having at least one capacitor structure formed on a surface, the capacitor structure having a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material has columnar grains.Type: GrantFiled: January 10, 2008Date of Patent: February 2, 2010Assignee: Intel CorporationInventors: Cengiz A. Palanduz, Dustin P. Wood
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Patent number: 7524754Abstract: In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.Type: GrantFiled: December 27, 2005Date of Patent: April 28, 2009Assignee: Intel CorporationInventors: Mark Bohr, Jun He, Fay Hua, Dustin P. Wood
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Patent number: 7495336Abstract: An integrated broadband array capacitor includes at least two regions with varying capacitance and response times. The broadband array capacitor is disposable on a socket or is integral with a socket. A method of operating the broadband array capacitor includes responding to load transients from each of the at least two regions. A computing system is also disclosed that includes the broadband array capacitor.Type: GrantFiled: December 30, 2005Date of Patent: February 24, 2009Assignee: Intel CorporationInventors: Joel A. Auernheimer, Nicholas Holmberg, Kaladhar Radhakrishnan, Dustin P. Wood
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Patent number: 7463492Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.Type: GrantFiled: June 26, 2007Date of Patent: December 9, 2008Assignee: Intel CorporationInventors: Kaladhar Radhakrishnan, Dustin P. Wood, Nicholas L. Holmberg
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Publication number: 20080142962Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.Type: ApplicationFiled: February 28, 2008Publication date: June 19, 2008Inventors: Brent S. Stone, Dustin P. Wood, Kaladhar Radhakrishnan
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Publication number: 20080136010Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.Type: ApplicationFiled: January 30, 2008Publication date: June 12, 2008Inventors: Dustin P. Wood, Kaladhar Radhakrishnan
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Patent number: 7375412Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.Type: GrantFiled: March 31, 2005Date of Patent: May 20, 2008Assignee: Intel CorporationInventors: Cengiz A. Palanduz, Dustin P. Wood
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Patent number: 7365428Abstract: An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, one or more traces, and a second plurality of contacts disposed on the first side. The second plurality of contacts are adapted to engage with a second corresponding plurality of contacts on the external integrated circuit package, wherein at least two of the second plurality of contacts are adapted to be coupled to at least a first trace of the one or more traces to form a first resistive structure.Type: GrantFiled: October 22, 2004Date of Patent: April 29, 2008Assignee: Intel CorporationInventors: Joel A. Auernheimer, Nicholas L. Holmberg, Kaladhar Radhakrishnan, Dustin P. Wood
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Patent number: 7355836Abstract: An array capacitor is provided. The array capacitor includes a plurality of ground planes inside a dielectric substrate, and a plurality of ground vias. The ground vias electrically connect the ground planes together. Further, the ground vias are connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals. The array capacitor further includes a plurality of power planes inside the dielectric substrate. The power planes and the ground planes are arranged alternatively inside the dielectric substrate. Each power plane comprises a plurality of power-plane-sections which are mutually electrically isolated. The array capacitor also includes a plurality of power vias which electrically connect the power planes together. Further, the power vias are connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.Type: GrantFiled: June 7, 2005Date of Patent: April 8, 2008Assignee: Intel CorporationInventors: Kaladhar Radhakrishnan, Nicholas L Holmberg, Joel A Auernheimer, Dustin P Wood
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Patent number: 7348214Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.Type: GrantFiled: January 11, 2007Date of Patent: March 25, 2008Assignee: Intel CorporationInventors: Dustin P. Wood, Kaladhar Radhakrishnan
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Patent number: 7339263Abstract: An integrated circuit package includes a first capacitor supported by a surface of a substrate, and a second capacitor supported by the surface of the substrate. The first capacitor is within a die shadow region, and the second capacitor lies outside of the die shadow region.Type: GrantFiled: June 28, 2004Date of Patent: March 4, 2008Assignee: Intel CorporationInventors: Brent S. Stone, Dustin P. Wood, Kaladhar Radhakrishnan
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Patent number: 7321172Abstract: In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.Type: GrantFiled: September 14, 2005Date of Patent: January 22, 2008Assignee: Intel CorporationInventors: Dustin P. Wood, Debendra Mallik
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Patent number: 7265995Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.Type: GrantFiled: December 29, 2003Date of Patent: September 4, 2007Assignee: Intel CorporationInventors: Kaladhar Radhakrishnan, Dustin P. Wood, Nicholas L. Holmberg