Abstract: Apparatus and methods are provided for a rigid metal core carrier substrate. The metal core increases the modulus of elasticity of the carrier substrate to greater than 20 GPa to better resist bending loads and stresses encountered during assembly, testing and consumer handling. The carrier substrate negates the need to provide external stiffening members resulting in a microelectronic package of reduced size and complexity. The coefficient of thermal expansion of the carrier substrate can be adapted to more closely match that of the microelectronic die, providing a device more resistant to thermally-induced stresses. In one embodiment of the method in accordance with the invention, a metal sheet having a thickness in the range including 200-500 &mgr;m and a flexural modulus of elasticity of at least 20 GPa is laminated on both sides with dielectric and conductive materials using standard processing technologies to create a carrier substrate.

Abstract: In one embodiment there is provided a motherboard assembly. The motherboard assembly comprises a motherboard substrate; a conductive circuit on a first side of the motherboard substrate comprising an interface to connect the conductive circuit to an electrical component; and a power leveling element aligned with the interface and mounted to a second side of the motherboard substrate opposite the first side, the power leveling element being to level power delivery from the interface.

Abstract: An integrated circuit chip package having a metal substrate core having two or more electrically isolated regions, wherein the electrically isolated regions of the metal substrate core may be coupled with voltage rails of an integrated circuit chip.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.