Abstract: Audio content in a single-bit audio stream can be reproduced at a transducer by mapping the single-bit audio stream to symbols in a multi-bit audio stream. Volume control may be implemented, in part, in the digital domain and, in part, in the analog domain. In the digital domain, when converting the single-bit audio stream to a plurality of symbols, the plurality of symbols is selected based, at least in part, on audio content of the single-bit audio stream and a desired volume level. In the analog domain, when converting an analog current signal output from a current-steering DAC processing the plurality of symbols to an analog voltage signal, an analog gain value may be selected based, at least in part, on the desired volume level.

Abstract: An audio processing circuit may have a first path for processing multi-bit audio signals in parallel with a second path for processing single-bit audio signals. The parallel paths may share a common input node for receiving audio data and a common output node for reproducing audio at a transducer. Each path may have a volume control for adjusting an output of the path. The audio processing circuit may determine a type of an audio signal received at the input. The path not corresponding to the detected type of the audio signal is muted, and the path corresponding to the detected type of audio signal is unmuted.

Abstract: A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

Abstract: A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

Abstract: Audio content in a single-bit audio stream can be reproduced at a transducer by mapping the single-bit audio stream to symbols in a multi-bit audio stream. Volume control may be implemented, in part, in the digital domain and, in part, in the analog domain. In the digital domain, when converting the single-bit audio stream to a plurality of symbols, the plurality of symbols is selected based, at least in part, on audio content of the single-bit audio stream and a desired volume level. In the analog domain, when converting an analog current signal output from a current-steering DAC processing the plurality of symbols to an analog voltage signal, an analog gain value may be selected based, at least in part, on the desired volume level.

Abstract: An audio processing circuit may have a first path for processing multi-bit audio signals in parallel with a second path for processing single-bit audio signals. The parallel paths may share a common input node for receiving audio data and a common output node for reproducing audio at a transducer. Each path may have a volume control for adjusting an output of the path. The audio processing circuit may determine a type of an audio signal received at the input. The path not corresponding to the detected type of the audio signal is muted, and the path corresponding to the detected type of audio signal is unmuted.

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract: A technique includes selectively coupling impedances to an oscillator to establish a first frequency of operation of the oscillator. The technique includes repeating the selective coupling in a feedback loop to cause the first frequency to be near a second frequency.

Abstract: A technique includes generating an analog voltage to control a frequency for an oscillator. The analog signal is converted into a digital signal, and the frequency is controlled in response to the digital signal.

Abstract: A bias system is disclosed including a calibration bus to which a controller, a reference bias source, a master bias source, and first and second slave bias sources are coupled. The controller varies a control code sent over the calibration bus to the master bias source until a particular control code is found that causes the bias signal of the master bias source to equal a desired bias value which is provided by the reference bias source. The controller then sends the particular control code to the first and second slave bias sources to cause the first and second slave bias sources to generate a bias signal having the same desired bias value as the master bias source.

Abstract: A bias system is disclosed including a calibration bus to which a controller, a reference bias source, a master bias source, and first and second slave bias sources are coupled. The controller varies a control code sent over the calibration bus to the master bias source until a particular control code is found that causes the bias signal of the master bias source to equal a desired bias value which is provided by the reference bias source. The controller then sends the particular control code to the first and second slave bias sources to cause the first and second slave bias sources to generate a bias signal having the same desired bias value as the master bias source. Isolation between load circuits coupled to the first and second bias sources is thus enhanced while providing low noise, stable operation.

Abstract: A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.

Abstract: Digital-to-analog conversion circuitry 100 is shown including a path for processing data in a 1-bit format. First portion of an analog finite impulse response filter 300 includes pre-selected number of delay elements 301 for receiving stream of data in the 1-bit format and outputting a plurality of signals in response. A switched capacitor digital-to-analog converter 106 forms a second portion of the finite impulse response filter 301 and has a plurality of elements each receiving one of the plurality of signals as selected to effectuate a set of filter coefficients, converter 106 summing the plurality of signals and outputting an analog data stream.