Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract: This application is in the field of sialic acid chemistry, metabolism, antigenicity, and the production of transgenic non-human mammals with altered sialic acid production. More particularly, this application relates to N-glycolylneuraminic acid (Neu5Gc) being an immunogen in humans, and the production of Neu5Gc-free mammalian products for laboratory and human use.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract: System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption.

Abstract: System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

Abstract: This application is in the field of sialic acid chemistry, metabolism, antigenicity, and the production of transgenic non-human mammals with altered sialic acid production. More particularly, this application relates to N-glycolylneuraminic acid (Neu5Gc) being an immunogen in humans, and the production of Neu5Gc-free mammalian products for laboratory and human use.

Abstract: System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory command is received at each non-volatile memory concurrently. The memory command is initiated at different times relative to receiving the global memory command for at least two of the plurality of non-volatile memory to mitigate peak power consumption.

Abstract: This disclosure relates to methods for modulating lymphocyte activity and/or proliferation by regulating the activity or expression of Siglec.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract: The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is closer to the top of the column, the SG(D) line is biased prior to the SG(S) line. If the cell is closer to the bottom of the column, the SG(S) line is biased prior to the SG(D) line.

Abstract: Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND flash memory devices. The boosted voltage can be used as a gate voltage for a pass gate providing programming voltages to a selected block of memory cells, such as in a NAND flash memory array. The pass circuits facilitate the elimination of high-voltage p-channel devices by providing a boosted voltage using n-channel devices. The pass circuits further permit control of multiple pass gates using a single boosted voltage source.

Abstract: Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND flash memory devices. The boosted voltage can be used as a gate voltage for a pass gate providing programming voltages to a selected block of memory cells, such as in a NAND flash memory array. The pass circuits facilitate the elimination of high-voltage p-channel devices by providing a boosted voltage using n-channel devices. The pass circuits further permit control of multiple pass gates using a single boosted voltage source.

Abstract: The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is closer to the top of the column, the SG(D) line is biased prior to the SG(S) line. If the cell is closer to the bottom of the column, the SG(S) line is biased prior to the SG(D) line.

Abstract: A quick change, self-contained vacuum system includes a debris container with an input opening and a pressure head that is configured to receive a fluid under a high pressure and which includes a low pressure inlet and an exhaust port. A guide pin may be provided along with a body that is selectively engageable with the pressure head and the guide pin. The body includes a bore having a first port communicating with the exhaust port of the pressure head and a second port communicating with the input opening of the debris container. The vacuum system further includes a shutoff valve that is operable in response to movement of the guide pin. In operation, movement of the guide pin relative to the body in one direction establishes locking engagement of the pressure head and the body along with a response by the shutoff valve to establish fluid communication between the exhaust port of the pressure head and the input opening of the debris container.

Abstract: A quick change, self-contained vacuum system includes a debris container with an input opening and a pressure head that is configured to receive a fluid under a high pressure and which includes a low pressure inlet and an exhaust port. A guide pin may be provided along with a body that is selectively engageable with the pressure head and the guide pin. The body includes a bore having a first port communicating with the exhaust port of the pressure head and a second port communicating with the input opening of the debris container. The vacuum system further includes a shutoff valve that is operable in response to movement of the guide pin. In operation, movement of the guide pin relative to the body in one direction establishes locking engagement of the pressure head and the body along with a response by the shutoff valve to establish fluid communication between the exhaust port of the pressure head and the input opening of the debris container.

Abstract: A method for reducing the die size of an integrated circuit by locating, on one of the four sides of the perimeter of an IC die, only the bonding pads (`standard I/O pads`) which provide I/O functionality and which must occupy a predetermined location in accordance with an industry-standard. The active support circuit associated with each of these standard I/O pads is located on one or more of the three other sides at external connection locations which are otherwise unused, or `spare`. The standard I/O pads on the first side of the IC die are connected, via wires, to the corresponding support circuitry on the other sides of the die.

Abstract: A centralizer for downhole sucker rods such as those used in oil wells. The centralizer has a central axial aperture for rotatable mounting on a downhole rod of a rod string. The exterior surface of the centralizer is shaped to engage the well wall when brought into contact with the wall such that rotational movement of the centralizer is limited or stopped with respect to the wall. Generally, the exterior of the centralizer is shaped to match the shape of the wall of the well in which it is to be used. A centralizer for use with a well lined with a circular tubing thus has at least one exterior surface which in cross section defines an arc having a radius of curvature equal to that of the tubing interior. A disclosed embodiment has six lobes having surfaces defining in cross section portions of three such arcs arranged symmetrically about the central aperture.